Partially Reconfigurable Platforms
Embedded Systems-on-Chip comprised of traditional computing engines and tightly-coupled reprogrammable logic (FPGA) are a game-changer. Their versatility opens the doors for new computational paradigms; to rethink traditional software/hardware stacks. In our lab, we are investigating the degrees of self-awareness that can be attained via FPGA-in-the-middle performance assessment and control.
Projects
PLIM: Programmable Logic In the Middle
Programmable logic placed between the processor and main memory, where every memory transaction can be inspected and manipulated.
Relational Memory Controller
Hardware that reorganizes data layout on the fly, so software can read any group of columns from row-oriented data.
17 publications in this area
- Programmable Data Layouts via On-The-Fly Data Transformation
- Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems
- Devil-in-FPGA: Coherent Trojans in Reconfigurable Heterogeneous Systems
- FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging
- Burning Fetch Execution: A Framework for Zero-Trust Multi-party Confidential Computing
- RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms
- Micro-architectural Exploration of the Relational Memory Engine (RME) in RISC-V and FireSim
- UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms
- Effortless Locality on Data Systems Using Relational Fabric
- Software-Shaped Platforms
- Relational Fabric: Transparent Data Transformation
- Relational Memory: Native In-Memory Accesses on Rows and Columns
- CAESAR: Coherence-Aided Elective and Seamless Alternative Routing via on-chip FPGA
- Hardware Data Re-organization Engine for Real-Time Systems
- A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic
- Reconciling Predictability and Coherent Caching
- The Potential of Programmable Logic in the Middle: Cache Bleaching