About
Denis Hoornaert is a long-time collaborator and co-author of the lab. His work with the lab centers on hardware/software co-design on CPU+FPGA platforms: memory scheduling in programmable logic (SchIM), mixed-criticality task-based isolation (MCTI), CAESAR, Relational Memory, and the UltraScale+ SpinalHDL Wrapper.
Code and hardware artifacts
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MemorEDF Software and hardware Maintainer
Demonstration of combined CPU and memory regulation on a Zynq UltraScale+ board. -
UltraScale+ SpinalHDL Wrapper Hardware design Maintainer
Support library that takes SpinalHDL designs to a bitstream on UltraScale+ platforms. -
RT-Bench Software Co-author of the paper that introduced it
An extensible framework that turns existing benchmarks into periodic real-time workloads. -
Relational Memory Engine on FireSim Hardware design Co-author of the paper that introduced it
FireSim setup of the Relational Memory Engine with RISC-V Rocket and BOOM cores.
21 publications with the lab
- Burning Fetch Execution: A Framework for Zero-Trust Multi-party Confidential Computing
- RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms
- Micro-architectural Exploration of the Relational Memory Engine (RME) in RISC-V and FireSim
- RT-Bench: A Long Overdue Update
- Surgical Software-less I/O Virtualization
- UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms
- Coherence-Aided Memory Bandwidth Regulation
- MCTI: Mixed-Criticality Task-based Isolation
- Effortless Locality on Data Systems Using Relational Fabric
- Low-overhead Online Assessment of Timely Progress as a System Commodity
- Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs
- Software-Shaped Platforms
- Relational Fabric: Transparent Data Transformation
- Relational Memory: Native In-Memory Accesses on Rows and Columns
- CAESAR: Coherence-Aided Elective and Seamless Alternative Routing via on-chip FPGA
- Hardware Data Re-organization Engine for Real-Time Systems
- Know your Enemy: Benchmarking and Experimenting with Insight as a Goal
- On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems
- RT-Bench: An Extensible Benchmark Framework for the Analysis and Management of Real-Time Applications
- A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic
- Identifying Unexpected Inter-core Interference Induced by Shared Cache