Publications Partially Reconfigurable Platforms
A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic
33rd Euromicro Conference on Real-Time Systems (ECRTS 2021), July 2021, Stuttgart, Germany
Abstract
The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing Systems (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and re-configurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor. This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks.
Code and hardware artifacts
Cite this paper
@inproceedings{SchIM_ECRTS21,
title = {{A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic}},
author = {Hoornaert, Denis and Roozkhosh, Shahin and Mancuso, Renato},
booktitle = {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
year = 2021,
month = jul,
volume = {196},
pages = {2:1--2:22},
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Stuttgart, Germany},
doi = {10.4230/LIPIcs.ECRTS.2021.2},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2021.2}
}
TY - CONF AU - Hoornaert, Denis AU - Roozkhosh, Shahin AU - Mancuso, Renato TI - A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic T2 - 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021) PY - 2021 DA - 2021/07// VL - 196 PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Stuttgart, Germany SP - 2:1 EP - 2:22 DO - 10.4230/LIPIcs.ECRTS.2021.2 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2021.2 AB - The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing Systems (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and re-configurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor. This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks. ER -
%0 Conference Paper %A Hoornaert, Denis %A Roozkhosh, Shahin %A Mancuso, Renato %T A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic %B 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021) %D 2021 %V 196 %P 2:1-2:22 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Stuttgart, Germany %R 10.4230/LIPIcs.ECRTS.2021.2 %U https://doi.org/10.4230/LIPIcs.ECRTS.2021.2 %X The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing Systems (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and re-configurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor. This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks.
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"abstract": "The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has lead to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing Systems (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and re-configurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor. This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks."
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D. Hoornaert, S. Roozkhosh, and R. Mancuso, “A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic,” in 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021), vol. 196, pp. 2:1–2:22, Jul. 2021, doi: 10.4230/LIPIcs.ECRTS.2021.2.
Hoornaert, D., Roozkhosh, S., & Mancuso, R. (2021). A Memory Scheduling Infrastructure for Multi-core Systems with Re-programmable Logic. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021) (pp. 2:1–2:22). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2021.2