Publications Partially Reconfigurable Platforms
FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging
5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026, May 2026, Saint Malo, France
Abstract
Fine-grained tracing of memory activity is useful for analyzing software behavior and understanding software-hardware interactions. Existing approaches rely either on software instrumentation, which introduces high overhead, or on architecture-specific hardware tracing mechanisms with limited flexibility and filtering capabilities. In particular, current solutions provide limited support for process-specific filtering and/or simultaneous visibility of virtual and physical addresses. This paper presents FRACTAL, a hardware module that operates in the coherence domain and enables tracing of memory transactions for a target process. FRACTAL passively observes coherence traffic and performs reverse address translation to reconstruct virtual addresses from physical memory accesses. To achieve this, it follows the page table walks of the monitored process and maintains a reverse translation structure that mirrors the processor TLB. The design is largely microarchitectureagnostic, does not require binary instrumentation, and does not affect the performance of the traced application. We implement FRACTAL on a commercial heterogeneous multiprocessor system-on-chip platform, the KRIA KV260, with programmable logic integrated in the cache-coherent interconnect. Experimental evaluation using vision benchmarks shows that the system can do fine-grained tracing of selected virtual address ranges with negligible overhead. The results demonstrate that coherence-based observation combined with reverse translation is a practical approach for low-intrusion memory tracing.
Code and hardware artifacts
Cite this paper
@inproceedings{FRACTAL_RAGE26,
title = {{FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging}},
author = {Ciraolo, Francesco and Carpanedo, Patrick and Ottaviano, Daniele and Ou, Matias and Caccamo, Marco and Mancuso, Renato},
booktitle = {5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026},
year = 2026,
month = may,
publisher = {Association for Computing Machinery},
address = {Saint Malo, France},
url = {https://cs-people.bu.edu/rmancuso/files/papers/FRACTAL_RAGE26.pdf}
}
TY - CONF AU - Ciraolo, Francesco AU - Carpanedo, Patrick AU - Ottaviano, Daniele AU - Ou, Matias AU - Caccamo, Marco AU - Mancuso, Renato TI - FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging T2 - 5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026 PY - 2026 DA - 2026/05// PB - Association for Computing Machinery CY - Saint Malo, France AB - Fine-grained tracing of memory activity is useful for analyzing software behavior and understanding software-hardware interactions. Existing approaches rely either on software instrumentation, which introduces high overhead, or on architecture-specific hardware tracing mechanisms with limited flexibility and filtering capabilities. In particular, current solutions provide limited support for process-specific filtering and/or simultaneous visibility of virtual and physical addresses. This paper presents FRACTAL, a hardware module that operates in the coherence domain and enables tracing of memory transactions for a target process. FRACTAL passively observes coherence traffic and performs reverse address translation to reconstruct virtual addresses from physical memory accesses. To achieve this, it follows the page table walks of the monitored process and maintains a reverse translation structure that mirrors the processor TLB. The design is largely microarchitectureagnostic, does not require binary instrumentation, and does not affect the performance of the traced application. We implement FRACTAL on a commercial heterogeneous multiprocessor system-on-chip platform, the KRIA KV260, with programmable logic integrated in the cache-coherent interconnect. Experimental evaluation using vision benchmarks shows that the system can do fine-grained tracing of selected virtual address ranges with negligible overhead. The results demonstrate that coherence-based observation combined with reverse translation is a practical approach for low-intrusion memory tracing. ER -
%0 Conference Paper %A Ciraolo, Francesco %A Carpanedo, Patrick %A Ottaviano, Daniele %A Ou, Matias %A Caccamo, Marco %A Mancuso, Renato %T FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging %B 5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026 %D 2026 %I Association for Computing Machinery %C Saint Malo, France %X Fine-grained tracing of memory activity is useful for analyzing software behavior and understanding software-hardware interactions. Existing approaches rely either on software instrumentation, which introduces high overhead, or on architecture-specific hardware tracing mechanisms with limited flexibility and filtering capabilities. In particular, current solutions provide limited support for process-specific filtering and/or simultaneous visibility of virtual and physical addresses. This paper presents FRACTAL, a hardware module that operates in the coherence domain and enables tracing of memory transactions for a target process. FRACTAL passively observes coherence traffic and performs reverse address translation to reconstruct virtual addresses from physical memory accesses. To achieve this, it follows the page table walks of the monitored process and maintains a reverse translation structure that mirrors the processor TLB. The design is largely microarchitectureagnostic, does not require binary instrumentation, and does not affect the performance of the traced application. We implement FRACTAL on a commercial heterogeneous multiprocessor system-on-chip platform, the KRIA KV260, with programmable logic integrated in the cache-coherent interconnect. Experimental evaluation using vision benchmarks shows that the system can do fine-grained tracing of selected virtual address ranges with negligible overhead. The results demonstrate that coherence-based observation combined with reverse translation is a practical approach for low-intrusion memory tracing.
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"abstract": "Fine-grained tracing of memory activity is useful for analyzing software behavior and understanding software-hardware interactions. Existing approaches rely either on software instrumentation, which introduces high overhead, or on architecture-specific hardware tracing mechanisms with limited flexibility and filtering capabilities. In particular, current solutions provide limited support for process-specific filtering and/or simultaneous visibility of virtual and physical addresses. This paper presents FRACTAL, a hardware module that operates in the coherence domain and enables tracing of memory transactions for a target process. FRACTAL passively observes coherence traffic and performs reverse address translation to reconstruct virtual addresses from physical memory accesses. To achieve this, it follows the page table walks of the monitored process and maintains a reverse translation structure that mirrors the processor TLB. The design is largely microarchitectureagnostic, does not require binary instrumentation, and does not affect the performance of the traced application. We implement FRACTAL on a commercial heterogeneous multiprocessor system-on-chip platform, the KRIA KV260, with programmable logic integrated in the cache-coherent interconnect. Experimental evaluation using vision benchmarks shows that the system can do fine-grained tracing of selected virtual address ranges with negligible overhead. The results demonstrate that coherence-based observation combined with reverse translation is a practical approach for low-intrusion memory tracing."
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F. Ciraolo, P. Carpanedo, D. Ottaviano, M. Ou, M. Caccamo, and R. Mancuso, “FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging,” in 5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026, May. 2026.
Ciraolo, F., Carpanedo, P., Ottaviano, D., Ou, M., Caccamo, M., & Mancuso, R. (2026). FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging. In 5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026. Association for Computing Machinery.