Publications Partially Reconfigurable Platforms Memory & Shared-Resource Management
Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems
47th IEEE Real-Time Systems Symposium (RTSS 2026), December 2026, Yokohama, Japan To appear
Abstract
Memory bandwidth regulation is critical for predictability on multi-core systems, where co-running tasks interfere through shared memory resources. Existing approaches typically regulate bandwidth at the core or system level. They often assume a single shared memory controller, without distinguishing which parts of a complex, potentially heterogeneous memory subsystem are being stressed. This paper introduces a bottleneck-aware bandwidth regulation approach for heterogeneous memory subsystems that combines spatial task separation, runtime bandwidth observation and regulation, and a general theoretical shared-resource model to reason about bandwidth guarantees. We implement our system on a Xilinx Zynq UltraScale+ ZCU102 platform and evaluate it on bankpartitioned workloads. Compared to conservative bank-oblivious regulation techniques, our approach preserves the guaranteed bandwidth of protected tasks while imposing less restrictive limits on co-runners, increasing total system bandwidth. Overall, this work introduces novel bottleneck-aware regulation that improves shared resource utilization without sacrificing the ability to reason about guarantees.
Code and hardware artifacts
Cite this paper
@inproceedings{HeterCoRe_RTSS26,
title = {{Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems}},
author = {Izhbirdeev, Ivan and Chen, Weifan and Yun, Heechul and Mancuso, Renato},
booktitle = {47th IEEE Real-Time Systems Symposium (RTSS 2026)},
year = 2026,
month = dec,
address = {Yokohama, Japan},
url = {https://cs-people.bu.edu/rmancuso/files/papers/HeterCoRe_RTSS26.pdf}
}
TY - CONF AU - Izhbirdeev, Ivan AU - Chen, Weifan AU - Yun, Heechul AU - Mancuso, Renato TI - Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems T2 - 47th IEEE Real-Time Systems Symposium (RTSS 2026) PY - 2026 DA - 2026/12// CY - Yokohama, Japan AB - Memory bandwidth regulation is critical for predictability on multi-core systems, where co-running tasks interfere through shared memory resources. Existing approaches typically regulate bandwidth at the core or system level. They often assume a single shared memory controller, without distinguishing which parts of a complex, potentially heterogeneous memory subsystem are being stressed. This paper introduces a bottleneck-aware bandwidth regulation approach for heterogeneous memory subsystems that combines spatial task separation, runtime bandwidth observation and regulation, and a general theoretical shared-resource model to reason about bandwidth guarantees. We implement our system on a Xilinx Zynq UltraScale+ ZCU102 platform and evaluate it on bankpartitioned workloads. Compared to conservative bank-oblivious regulation techniques, our approach preserves the guaranteed bandwidth of protected tasks while imposing less restrictive limits on co-runners, increasing total system bandwidth. Overall, this work introduces novel bottleneck-aware regulation that improves shared resource utilization without sacrificing the ability to reason about guarantees. ER -
%0 Conference Paper %A Izhbirdeev, Ivan %A Chen, Weifan %A Yun, Heechul %A Mancuso, Renato %T Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems %B 47th IEEE Real-Time Systems Symposium (RTSS 2026) %D 2026 %C Yokohama, Japan %X Memory bandwidth regulation is critical for predictability on multi-core systems, where co-running tasks interfere through shared memory resources. Existing approaches typically regulate bandwidth at the core or system level. They often assume a single shared memory controller, without distinguishing which parts of a complex, potentially heterogeneous memory subsystem are being stressed. This paper introduces a bottleneck-aware bandwidth regulation approach for heterogeneous memory subsystems that combines spatial task separation, runtime bandwidth observation and regulation, and a general theoretical shared-resource model to reason about bandwidth guarantees. We implement our system on a Xilinx Zynq UltraScale+ ZCU102 platform and evaluate it on bankpartitioned workloads. Compared to conservative bank-oblivious regulation techniques, our approach preserves the guaranteed bandwidth of protected tasks while imposing less restrictive limits on co-runners, increasing total system bandwidth. Overall, this work introduces novel bottleneck-aware regulation that improves shared resource utilization without sacrificing the ability to reason about guarantees.
[
{
"id": "HeterCoRe_RTSS26",
"type": "paper-conference",
"title": "Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems",
"author": [
{
"family": "Izhbirdeev",
"given": "Ivan"
},
{
"family": "Chen",
"given": "Weifan"
},
{
"family": "Yun",
"given": "Heechul"
},
{
"family": "Mancuso",
"given": "Renato"
}
],
"container-title": "47th IEEE Real-Time Systems Symposium (RTSS 2026)",
"issued": {
"date-parts": [
[
2026,
12
]
]
},
"publisher-place": "Yokohama, Japan",
"abstract": "Memory bandwidth regulation is critical for predictability on multi-core systems, where co-running tasks interfere through shared memory resources. Existing approaches typically regulate bandwidth at the core or system level. They often assume a single shared memory controller, without distinguishing which parts of a complex, potentially heterogeneous memory subsystem are being stressed. This paper introduces a bottleneck-aware bandwidth regulation approach for heterogeneous memory subsystems that combines spatial task separation, runtime bandwidth observation and regulation, and a general theoretical shared-resource model to reason about bandwidth guarantees. We implement our system on a Xilinx Zynq UltraScale+ ZCU102 platform and evaluate it on bankpartitioned workloads. Compared to conservative bank-oblivious regulation techniques, our approach preserves the guaranteed bandwidth of protected tasks while imposing less restrictive limits on co-runners, increasing total system bandwidth. Overall, this work introduces novel bottleneck-aware regulation that improves shared resource utilization without sacrificing the ability to reason about guarantees."
}
]
I. Izhbirdeev, W. Chen, H. Yun, and R. Mancuso, “Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems,” in 47th IEEE Real-Time Systems Symposium (RTSS 2026), Dec. 2026.
Izhbirdeev, I., Chen, W., Yun, H., & Mancuso, R. (2026). Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems. In 47th IEEE Real-Time Systems Symposium (RTSS 2026).