Publications Partially Reconfigurable Platforms
Programmable Data Layouts via On-The-Fly Data Transformation
32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027), April 2027, Heraklion, Crete, Greece To appear
Abstract
The performance of modern computing systems is heavily bottlenecked by the widening gap between processing throughput and main memory latency, a problem exacerbated when an application’s logical data access patterns misalign with the physical layout of data in memory. To address this, we propose a hardware-software co-design framework comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU). DTL allows programmers to concisely express complex data layout reorganizations, which the compiler translates into efficient hardware routing configurations. The DTU, a hardware engine logically situated between the Last-Level Cache (LLC) and main memory, transparently evaluates these configurations on-the-fly to gather scattered data elements into dense, logically contiguous cache lines. By converting explicit layout transformations into virtual views, this approach eliminates the need for explicit data materialization in software. We evaluate the DTU within a quad-core RISC-V SoC using FireSim, demonstrating substantial improvements in execution speed and memory efficiency.
Cite this paper
@inproceedings{DTU_ASPLOS27,
title = {{Programmable Data Layouts via On-The-Fly Data Transformation}},
author = {Strickler, Cole and Athanassoulis, Manos and Mancuso, Renato and Yun, Heechul},
booktitle = {32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027)},
year = 2027,
month = apr,
address = {Heraklion, Crete, Greece},
doi = {10.1145/3845814.3850077},
url = {https://doi.org/10.1145/3845814.3850077}
}
TY - CONF AU - Strickler, Cole AU - Athanassoulis, Manos AU - Mancuso, Renato AU - Yun, Heechul TI - Programmable Data Layouts via On-The-Fly Data Transformation T2 - 32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027) PY - 2027 DA - 2027/04// CY - Heraklion, Crete, Greece DO - 10.1145/3845814.3850077 UR - https://doi.org/10.1145/3845814.3850077 AB - The performance of modern computing systems is heavily bottlenecked by the widening gap between processing throughput and main memory latency, a problem exacerbated when an application’s logical data access patterns misalign with the physical layout of data in memory. To address this, we propose a hardware-software co-design framework comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU). DTL allows programmers to concisely express complex data layout reorganizations, which the compiler translates into efficient hardware routing configurations. The DTU, a hardware engine logically situated between the Last-Level Cache (LLC) and main memory, transparently evaluates these configurations on-the-fly to gather scattered data elements into dense, logically contiguous cache lines. By converting explicit layout transformations into virtual views, this approach eliminates the need for explicit data materialization in software. We evaluate the DTU within a quad-core RISC-V SoC using FireSim, demonstrating substantial improvements in execution speed and memory efficiency. ER -
%0 Conference Paper %A Strickler, Cole %A Athanassoulis, Manos %A Mancuso, Renato %A Yun, Heechul %T Programmable Data Layouts via On-The-Fly Data Transformation %B 32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027) %D 2027 %C Heraklion, Crete, Greece %R 10.1145/3845814.3850077 %U https://doi.org/10.1145/3845814.3850077 %X The performance of modern computing systems is heavily bottlenecked by the widening gap between processing throughput and main memory latency, a problem exacerbated when an application’s logical data access patterns misalign with the physical layout of data in memory. To address this, we propose a hardware-software co-design framework comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU). DTL allows programmers to concisely express complex data layout reorganizations, which the compiler translates into efficient hardware routing configurations. The DTU, a hardware engine logically situated between the Last-Level Cache (LLC) and main memory, transparently evaluates these configurations on-the-fly to gather scattered data elements into dense, logically contiguous cache lines. By converting explicit layout transformations into virtual views, this approach eliminates the need for explicit data materialization in software. We evaluate the DTU within a quad-core RISC-V SoC using FireSim, demonstrating substantial improvements in execution speed and memory efficiency.
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"DOI": "10.1145/3845814.3850077",
"abstract": "The performance of modern computing systems is heavily bottlenecked by the widening gap between processing throughput and main memory latency, a problem exacerbated when an application’s logical data access patterns misalign with the physical layout of data in memory. To address this, we propose a hardware-software co-design framework comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU). DTL allows programmers to concisely express complex data layout reorganizations, which the compiler translates into efficient hardware routing configurations. The DTU, a hardware engine logically situated between the Last-Level Cache (LLC) and main memory, transparently evaluates these configurations on-the-fly to gather scattered data elements into dense, logically contiguous cache lines. By converting explicit layout transformations into virtual views, this approach eliminates the need for explicit data materialization in software. We evaluate the DTU within a quad-core RISC-V SoC using FireSim, demonstrating substantial improvements in execution speed and memory efficiency."
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C. Strickler, M. Athanassoulis, R. Mancuso, and H. Yun, “Programmable Data Layouts via On-The-Fly Data Transformation,” in 32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027), Apr. 2027, doi: 10.1145/3845814.3850077.
Strickler, C., Athanassoulis, M., Mancuso, R., & Yun, H. (2027). Programmable Data Layouts via On-The-Fly Data Transformation. In 32nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2027). https://doi.org/10.1145/3845814.3850077