Publications Partially Reconfigurable Platforms
UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms
19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025), 2025, Brussels, Belgium
Abstract
In an embedded computing landscape that inexorably leans into heterogeneity, System-on-Chips (SoCs) featuring tightly integrated Field Programmable Gate Arrays (FPGA) are bound to proliferate. In particular, such architectures’ high degree of flexibility and control caters well to the real-time community. Despite the appeal, real-time research exploiting HW/SW co-design on such architectures has remained tepid. While the usual suspects, such as the complexity of Hardware Description Languages, can be blamed, recent advancements in tooling (e.g., languages, frameworks) have proven efficient in easing the design of FPGA-located accelerators. However, in the context of SoC with FPGA platforms, these solutions fall short of addressing the next hurdle: integrating the custom accelerators with the rest of the SoC, which requires the tedious implementation of various supporting software resources. This article presents the first iteration of the UltraScale+ SpinalHDL Wrapper; a SpinalHDL library dedicated to supporting HW/SW co-design on SoC with FPGA platforms. The support ranges from assisting during the design of accelerators to automatically inferring and generating ready-to-use software support, such as Linux Kernel modules and Vivado deployment scripts.
Code and hardware artifacts
Cite this paper
@inproceedings{USW_OSPERT25,
title = {{UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms}},
author = {Hoornaert, Denis and Corradi, Giulio and Mancuso, Renato and Caccamo, Marco},
booktitle = {19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025)},
year = 2025,
address = {Brussels, Belgium},
url = {https://cs-people.bu.edu/rmancuso/files/papers/USW_OSPERT25.pdf}
}
TY - CONF AU - Hoornaert, Denis AU - Corradi, Giulio AU - Mancuso, Renato AU - Caccamo, Marco TI - UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms T2 - 19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025) PY - 2025 CY - Brussels, Belgium AB - In an embedded computing landscape that inexorably leans into heterogeneity, System-on-Chips (SoCs) featuring tightly integrated Field Programmable Gate Arrays (FPGA) are bound to proliferate. In particular, such architectures’ high degree of flexibility and control caters well to the real-time community. Despite the appeal, real-time research exploiting HW/SW co-design on such architectures has remained tepid. While the usual suspects, such as the complexity of Hardware Description Languages, can be blamed, recent advancements in tooling (e.g., languages, frameworks) have proven efficient in easing the design of FPGA-located accelerators. However, in the context of SoC with FPGA platforms, these solutions fall short of addressing the next hurdle: integrating the custom accelerators with the rest of the SoC, which requires the tedious implementation of various supporting software resources. This article presents the first iteration of the UltraScale+ SpinalHDL Wrapper; a SpinalHDL library dedicated to supporting HW/SW co-design on SoC with FPGA platforms. The support ranges from assisting during the design of accelerators to automatically inferring and generating ready-to-use software support, such as Linux Kernel modules and Vivado deployment scripts. ER -
%0 Conference Paper %A Hoornaert, Denis %A Corradi, Giulio %A Mancuso, Renato %A Caccamo, Marco %T UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms %B 19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025) %D 2025 %C Brussels, Belgium %X In an embedded computing landscape that inexorably leans into heterogeneity, System-on-Chips (SoCs) featuring tightly integrated Field Programmable Gate Arrays (FPGA) are bound to proliferate. In particular, such architectures’ high degree of flexibility and control caters well to the real-time community. Despite the appeal, real-time research exploiting HW/SW co-design on such architectures has remained tepid. While the usual suspects, such as the complexity of Hardware Description Languages, can be blamed, recent advancements in tooling (e.g., languages, frameworks) have proven efficient in easing the design of FPGA-located accelerators. However, in the context of SoC with FPGA platforms, these solutions fall short of addressing the next hurdle: integrating the custom accelerators with the rest of the SoC, which requires the tedious implementation of various supporting software resources. This article presents the first iteration of the UltraScale+ SpinalHDL Wrapper; a SpinalHDL library dedicated to supporting HW/SW co-design on SoC with FPGA platforms. The support ranges from assisting during the design of accelerators to automatically inferring and generating ready-to-use software support, such as Linux Kernel modules and Vivado deployment scripts.
[
{
"id": "USW_OSPERT25",
"type": "paper-conference",
"title": "UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms",
"author": [
{
"family": "Hoornaert",
"given": "Denis"
},
{
"family": "Corradi",
"given": "Giulio"
},
{
"family": "Mancuso",
"given": "Renato"
},
{
"family": "Caccamo",
"given": "Marco"
}
],
"container-title": "19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025)",
"issued": {
"date-parts": [
[
2025
]
]
},
"publisher-place": "Brussels, Belgium",
"abstract": "In an embedded computing landscape that inexorably leans into heterogeneity, System-on-Chips (SoCs) featuring tightly integrated Field Programmable Gate Arrays (FPGA) are bound to proliferate. In particular, such architectures’ high degree of flexibility and control caters well to the real-time community. Despite the appeal, real-time research exploiting HW/SW co-design on such architectures has remained tepid. While the usual suspects, such as the complexity of Hardware Description Languages, can be blamed, recent advancements in tooling (e.g., languages, frameworks) have proven efficient in easing the design of FPGA-located accelerators. However, in the context of SoC with FPGA platforms, these solutions fall short of addressing the next hurdle: integrating the custom accelerators with the rest of the SoC, which requires the tedious implementation of various supporting software resources. This article presents the first iteration of the UltraScale+ SpinalHDL Wrapper; a SpinalHDL library dedicated to supporting HW/SW co-design on SoC with FPGA platforms. The support ranges from assisting during the design of accelerators to automatically inferring and generating ready-to-use software support, such as Linux Kernel modules and Vivado deployment scripts."
}
]
D. Hoornaert, G. Corradi, R. Mancuso, and M. Caccamo, “UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms,” in 19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025), 2025.
Hoornaert, D., Corradi, G., Mancuso, R., & Caccamo, M. (2025). UltraScale+ SpinalHDL Wrapper: Streamlining Ideas to Bitstream on UltraScale+ platforms. In 19th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2025).