Projects Partially Reconfigurable Platforms
PLIM: Programmable Logic In the Middle
Programmable logic placed between the processor and main memory, where every memory transaction can be inspected and manipulated.
PLIM interposes on-chip programmable logic between a multi-core processor and main memory, so individual memory transactions can be inspected and manipulated. Its first application, Cache Bleaching, removes a key shortcoming of page-coloring-based cache partitioning. The approach was evaluated on a Xilinx Zynq UltraScale+ ZCU102, and the paper received the Best Paper Award at RTAS 2020.