About
Weifan Chen is a Ph.D. student working on timeliness in multiprocessor systems-on-chip for hard real-time applications. His work covers online assessment of timely progress, progress-aware scheduling (CAPA), and memory bandwidth regulation.
Code and hardware artifacts
8 publications with the lab
- Bottleneck-Aware Bandwidth Regulation for Heterogeneous Memory Subsystems
- CAPA: A Framework for Contention-Aware and Progress-Aware Multi-Core Real-Time Systems
- Coherence-Aided Memory Bandwidth Regulation
- Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness
- MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation
- Low-overhead Online Assessment of Timely Progress as a System Commodity
- Investigating and Mitigating Contention on Low-End Multi-Core Microcontrollers
- MemPol: Policing Core Memory Bandwidth from Outside of the Cores