Publications Partially Reconfigurable Platforms
Cache Where you Want! Reconciling Predictability and Coherent Caching
, September 2019, Urbana, IL, USA
Abstract
Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.
Cite this paper
@inproceedings{bansal2019cache,
title = {{Cache Where you Want! Reconciling Predictability and Coherent Caching}},
author = {Bansal, Ayoosh and Singh, Jayati and Hao, Yifan and Wen, Jen-Yang and Mancuso, Renato and Caccamo, Marco},
year = 2019,
month = sep,
publisher = {University of Illinois at Urbana-Champaign (UIUC)},
address = {Urbana, IL, USA},
url = {https://arxiv.org/pdf/1909.05349}
}
TY - CONF AU - Bansal, Ayoosh AU - Singh, Jayati AU - Hao, Yifan AU - Wen, Jen-Yang AU - Mancuso, Renato AU - Caccamo, Marco TI - Cache Where you Want! Reconciling Predictability and Coherent Caching T2 - PY - 2019 DA - 2019/09// PB - University of Illinois at Urbana-Champaign (UIUC) CY - Urbana, IL, USA AB - Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance. ER -
%0 Conference Paper %A Bansal, Ayoosh %A Singh, Jayati %A Hao, Yifan %A Wen, Jen-Yang %A Mancuso, Renato %A Caccamo, Marco %T Cache Where you Want! Reconciling Predictability and Coherent Caching %B %D 2019 %I University of Illinois at Urbana-Champaign (UIUC) %C Urbana, IL, USA %X Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.
[
{
"id": "bansal2019cache",
"type": "paper-conference",
"title": "Cache Where you Want! Reconciling Predictability and Coherent Caching",
"author": [
{
"family": "Bansal",
"given": "Ayoosh"
},
{
"family": "Singh",
"given": "Jayati"
},
{
"family": "Hao",
"given": "Yifan"
},
{
"family": "Wen",
"given": "Jen-Yang"
},
{
"family": "Mancuso",
"given": "Renato"
},
{
"family": "Caccamo",
"given": "Marco"
}
],
"container-title": "",
"issued": {
"date-parts": [
[
2019,
9
]
]
},
"publisher": "University of Illinois at Urbana-Champaign (UIUC)",
"publisher-place": "Urbana, IL, USA",
"abstract": "Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance."
}
]
A. Bansal, J. Singh, Y. Hao, J. Y. Wen, R. Mancuso, and M. Caccamo, “Cache Where you Want! Reconciling Predictability and Coherent Caching,” in , Sep. 2019.
Bansal, A., Singh, J., Hao, Y., Wen, J. Y., Mancuso, R., & Caccamo, M. (2019). Cache Where you Want! Reconciling Predictability and Coherent Caching. In . University of Illinois at Urbana-Champaign (UIUC).