Publications Partially Reconfigurable Platforms
The Potential of Programmable Logic in the Middle: Cache Bleaching
26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020), April 2020, Sydney, Australia
Best Paper Award
Abstract
Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware re-designs, and by proposing software-only solutions to mitigate performance interference. Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.
Cite this paper
@inproceedings{PLIM20,
title = {{The Potential of Programmable Logic in the Middle: Cache Bleaching}},
author = {Roozkhosh, Shahin and Mancuso, Renato},
booktitle = {26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020)},
year = 2020,
month = apr,
address = {Sydney, Australia},
doi = {10.1109/RTAS48715.2020.00006},
url = {https://doi.org/10.1109/RTAS48715.2020.00006},
note = {Best Paper Award}
}
TY - CONF AU - Roozkhosh, Shahin AU - Mancuso, Renato TI - The Potential of Programmable Logic in the Middle: Cache Bleaching T2 - 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020) PY - 2020 DA - 2020/04// CY - Sydney, Australia DO - 10.1109/RTAS48715.2020.00006 UR - https://doi.org/10.1109/RTAS48715.2020.00006 AB - Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware re-designs, and by proposing software-only solutions to mitigate performance interference. Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach. ER -
%0 Conference Paper %A Roozkhosh, Shahin %A Mancuso, Renato %T The Potential of Programmable Logic in the Middle: Cache Bleaching %B 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020) %D 2020 %C Sydney, Australia %R 10.1109/RTAS48715.2020.00006 %U https://doi.org/10.1109/RTAS48715.2020.00006 %X Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware re-designs, and by proposing software-only solutions to mitigate performance interference. Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.
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"abstract": "Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware re-designs, and by proposing software-only solutions to mitigate performance interference. Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach."
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S. Roozkhosh and R. Mancuso, “The Potential of Programmable Logic in the Middle: Cache Bleaching,” in 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020), Apr. 2020, doi: 10.1109/RTAS48715.2020.00006.
Roozkhosh, S., & Mancuso, R. (2020). The Potential of Programmable Logic in the Middle: Cache Bleaching. In 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020). https://doi.org/10.1109/RTAS48715.2020.00006