CPSLab Cyber-Physical Systems Lab, Boston University

Publications Partially Reconfigurable Platforms

RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms

Patrick Carpanedo, Denis Hoornaert, Marco Caccamo, Renato Mancuso

46th IEEE Real-Time Systems Symposium (RTSS 2025), December 2025, Boston, USA

Read the PDF Code and artifacts Cite

Fig. 1. Overview of the demonstration setup and in-FPGA DoEth architecture. Trace data flows from the guest computer to the host computer. The data (1) originate from the CoreSight, (2) traverse the FPGA’s queue, the FrameFormer, and the ethernet controller, (3) reach the host over ethernet, and (4), finally, is picked up by the host using Wireshark and processed/displayed by our custom API.

Abstract

The abstract isn't on file yet. It is on the first page of the PDF.

Code and hardware artifacts

Cite this paper

@inproceedings{DoEth_RTSS25,
  title     = {{RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms}},
  author    = {Carpanedo, Patrick and Hoornaert, Denis and Caccamo, Marco and Mancuso, Renato},
  booktitle = {46th IEEE Real-Time Systems Symposium (RTSS 2025)},
  year      = 2025,
  month     = dec,
  address   = {Boston, USA},
  url       = {https://cs-people.bu.edu/rmancuso/files/papers/DoEth_RTSS25.pdf}
}

Download .bib