Publications Partially Reconfigurable Platforms
RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms
46th IEEE Real-Time Systems Symposium (RTSS 2025), December 2025, Boston, USA
Abstract
Efforts in systems design communities have produced static and online software methods for profiling and analysis purposes. Modern online approaches, such as RT-bench [1], rely on performance counters to track a limited amount of resource statistics related to the workload execution. This has the advantage of swiftly and faithfully representing the software/hardware interplay. However, a trade-off must always be found between granularity and overheads, as dedicated thread(s) must continuously pool and store the performance counters’ values. Furthermore, as the polling is asynchronous, the acquired data cannot be reliably mapped onto segments of the source code. We posit that an affordable and straightforward alternative exists. Our hardware/software co-designed approach named Debug over Ethernet (DoEth) takes advantage of the highly reprogrammable nature of modern SoC/FPGA platforms, such as the AMD-Xilinx UltraScale+ MPSoC series, to offer unmatched access to low-level activity of the SoC and privileged access to a plethora of high-performance peripherals. In this demonstration, we will briefly (1) outline our vision and (2) describe how our proposed prototype gathers fine-grained SoC’s activity information and makes it accessible to the end-user.
Code and hardware artifacts
Cite this paper
@inproceedings{DoEth_RTSS25,
title = {{RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms}},
author = {Carpanedo, Patrick and Hoornaert, Denis and Caccamo, Marco and Mancuso, Renato},
booktitle = {46th IEEE Real-Time Systems Symposium (RTSS 2025)},
year = 2025,
month = dec,
address = {Boston, USA},
url = {https://cs-people.bu.edu/rmancuso/files/papers/DoEth_RTSS25.pdf}
}
TY - CONF AU - Carpanedo, Patrick AU - Hoornaert, Denis AU - Caccamo, Marco AU - Mancuso, Renato TI - RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms T2 - 46th IEEE Real-Time Systems Symposium (RTSS 2025) PY - 2025 DA - 2025/12// CY - Boston, USA AB - Efforts in systems design communities have produced static and online software methods for profiling and analysis purposes. Modern online approaches, such as RT-bench [1], rely on performance counters to track a limited amount of resource statistics related to the workload execution. This has the advantage of swiftly and faithfully representing the software/hardware interplay. However, a trade-off must always be found between granularity and overheads, as dedicated thread(s) must continuously pool and store the performance counters’ values. Furthermore, as the polling is asynchronous, the acquired data cannot be reliably mapped onto segments of the source code. We posit that an affordable and straightforward alternative exists. Our hardware/software co-designed approach named Debug over Ethernet (DoEth) takes advantage of the highly reprogrammable nature of modern SoC/FPGA platforms, such as the AMD-Xilinx UltraScale+ MPSoC series, to offer unmatched access to low-level activity of the SoC and privileged access to a plethora of high-performance peripherals. In this demonstration, we will briefly (1) outline our vision and (2) describe how our proposed prototype gathers fine-grained SoC’s activity information and makes it accessible to the end-user. ER -
%0 Conference Paper %A Carpanedo, Patrick %A Hoornaert, Denis %A Caccamo, Marco %A Mancuso, Renato %T RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms %B 46th IEEE Real-Time Systems Symposium (RTSS 2025) %D 2025 %C Boston, USA %X Efforts in systems design communities have produced static and online software methods for profiling and analysis purposes. Modern online approaches, such as RT-bench [1], rely on performance counters to track a limited amount of resource statistics related to the workload execution. This has the advantage of swiftly and faithfully representing the software/hardware interplay. However, a trade-off must always be found between granularity and overheads, as dedicated thread(s) must continuously pool and store the performance counters’ values. Furthermore, as the polling is asynchronous, the acquired data cannot be reliably mapped onto segments of the source code. We posit that an affordable and straightforward alternative exists. Our hardware/software co-designed approach named Debug over Ethernet (DoEth) takes advantage of the highly reprogrammable nature of modern SoC/FPGA platforms, such as the AMD-Xilinx UltraScale+ MPSoC series, to offer unmatched access to low-level activity of the SoC and privileged access to a plethora of high-performance peripherals. In this demonstration, we will briefly (1) outline our vision and (2) describe how our proposed prototype gathers fine-grained SoC’s activity information and makes it accessible to the end-user.
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"abstract": "Efforts in systems design communities have produced static and online software methods for profiling and analysis purposes. Modern online approaches, such as RT-bench [1], rely on performance counters to track a limited amount of resource statistics related to the workload execution. This has the advantage of swiftly and faithfully representing the software/hardware interplay. However, a trade-off must always be found between granularity and overheads, as dedicated thread(s) must continuously pool and store the performance counters’ values. Furthermore, as the polling is asynchronous, the acquired data cannot be reliably mapped onto segments of the source code.\r\nWe posit that an affordable and straightforward alternative exists. Our hardware/software co-designed approach named Debug over Ethernet (DoEth) takes advantage of the highly reprogrammable nature of modern SoC/FPGA platforms, such as the AMD-Xilinx UltraScale+ MPSoC series, to offer unmatched access to low-level activity of the SoC and privileged access to a plethora of high-performance peripherals. In this demonstration, we will briefly (1) outline our vision and (2) describe how our proposed prototype gathers fine-grained SoC’s activity information and makes it accessible to the end-user."
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P. Carpanedo, D. Hoornaert, M. Caccamo, and R. Mancuso, “RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms,” in 46th IEEE Real-Time Systems Symposium (RTSS 2025), Dec. 2025.
Carpanedo, P., Hoornaert, D., Caccamo, M., & Mancuso, R. (2025). RTSS@Work: Toward Commodity Fine-grained Performance Tracing on ARM-based SoC/FPGA platforms. In 46th IEEE Real-Time Systems Symposium (RTSS 2025).