Publications Partially Reconfigurable Platforms
Reconciling Predictability and Coherent Caching
9th Mediterranean Conference on Embedded Computing (MECO 2020), June 2020, Budva, Montenegro
Abstract
Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.
Code and hardware artifacts
Cite this paper
@inproceedings{bansal2020cache,
title = {{Reconciling Predictability and Coherent Caching}},
author = {Bansal, Ayoosh and Singh, Jayati and Hao, Yifan and Wen, Jen-Yang and Mancuso, Renato and Caccamo, Marco},
booktitle = {9th Mediterranean Conference on Embedded Computing (MECO 2020)},
year = 2020,
month = jun,
pages = {1--6},
address = {Budva, Montenegro},
doi = {10.1109/MECO49872.2020.9134262},
url = {https://doi.org/10.1109/MECO49872.2020.9134262}
}
TY - CONF AU - Bansal, Ayoosh AU - Singh, Jayati AU - Hao, Yifan AU - Wen, Jen-Yang AU - Mancuso, Renato AU - Caccamo, Marco TI - Reconciling Predictability and Coherent Caching T2 - 9th Mediterranean Conference on Embedded Computing (MECO 2020) PY - 2020 DA - 2020/06// CY - Budva, Montenegro SP - 1 EP - 6 DO - 10.1109/MECO49872.2020.9134262 UR - https://doi.org/10.1109/MECO49872.2020.9134262 AB - Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance. ER -
%0 Conference Paper %A Bansal, Ayoosh %A Singh, Jayati %A Hao, Yifan %A Wen, Jen-Yang %A Mancuso, Renato %A Caccamo, Marco %T Reconciling Predictability and Coherent Caching %B 9th Mediterranean Conference on Embedded Computing (MECO 2020) %D 2020 %P 1-6 %C Budva, Montenegro %R 10.1109/MECO49872.2020.9134262 %U https://doi.org/10.1109/MECO49872.2020.9134262 %X Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.
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"abstract": "Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance."
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A. Bansal, J. Singh, Y. Hao, J. Y. Wen, R. Mancuso, and M. Caccamo, “Reconciling Predictability and Coherent Caching,” in 9th Mediterranean Conference on Embedded Computing (MECO 2020), pp. 1–6, Jun. 2020, doi: 10.1109/MECO49872.2020.9134262.
Bansal, A., Singh, J., Hao, Y., Wen, J. Y., Mancuso, R., & Caccamo, M. (2020). Reconciling Predictability and Coherent Caching. In 9th Mediterranean Conference on Embedded Computing (MECO 2020) (pp. 1–6). https://doi.org/10.1109/MECO49872.2020.9134262