Publications Memory & Shared-Resource Management
Coherence-Aided Memory Bandwidth Regulation
45th IEEE Real-Time Systems Symposium (RTSS 2024), December 2024, York, UK
Best Paper Award
Abstract
With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies. This work explores memory bandwidth regulation in such systems, leveraging the capabilities of tightly coupled FPGAs to offer elegant, low-overhead solutions with highly flexible regulation policies. We introduce MemCoRe, a novel approach that exploits the FPGA’s interaction with cache coherence interfaces and cross-trigger signals to achieve fine-grained spatiotemporal awareness of processor activity and software-free control. By comparing MemCoRe with state-of-the-art software-based approaches, namely MemGuard and MemPol, we demonstrate significant improvements in regulation precision and overhead reduction. Key contributions include nanosecond-scale memory bandwidth regulation, off-core memory bandwidth accounting, address-aware regulation, low-overhead token-bucket regulation, and asymmetric on-off core throttling. Our evaluation on a Xilinx Zynq UltraScale+ ZCU102 CPU+FPGA platform showcases MemCoRe’s capability to regulate memory bandwidth with nanosecond-scale precision. Overall, MemCoRe presents a promising avenue for efficient memory bandwidth regulation in PS-PL platforms, with strong applicability to real-time systems.
Code and hardware artifacts
Cite this paper
@inproceedings{memcore24,
title = {{Coherence-Aided Memory Bandwidth Regulation}},
author = {Izhbirdeev, Ivan and Hoornaert, Denis and Chen, Weifan and Zuepke, Alexander and Hammad, Youssef and Caccamo, Marco and Mancuso, Renato},
booktitle = {45th IEEE Real-Time Systems Symposium (RTSS 2024)},
year = 2024,
month = dec,
address = {York, UK},
url = {https://cs-people.bu.edu/rmancuso/files/papers/MemCoRe_RTSS24.pdf},
note = {Best Paper Award}
}
TY - CONF AU - Izhbirdeev, Ivan AU - Hoornaert, Denis AU - Chen, Weifan AU - Zuepke, Alexander AU - Hammad, Youssef AU - Caccamo, Marco AU - Mancuso, Renato TI - Coherence-Aided Memory Bandwidth Regulation T2 - 45th IEEE Real-Time Systems Symposium (RTSS 2024) PY - 2024 DA - 2024/12// CY - York, UK AB - With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies. This work explores memory bandwidth regulation in such systems, leveraging the capabilities of tightly coupled FPGAs to offer elegant, low-overhead solutions with highly flexible regulation policies. We introduce MemCoRe, a novel approach that exploits the FPGA’s interaction with cache coherence interfaces and cross-trigger signals to achieve fine-grained spatiotemporal awareness of processor activity and software-free control. By comparing MemCoRe with state-of-the-art software-based approaches, namely MemGuard and MemPol, we demonstrate significant improvements in regulation precision and overhead reduction. Key contributions include nanosecond-scale memory bandwidth regulation, off-core memory bandwidth accounting, address-aware regulation, low-overhead token-bucket regulation, and asymmetric on-off core throttling. Our evaluation on a Xilinx Zynq UltraScale+ ZCU102 CPU+FPGA platform showcases MemCoRe’s capability to regulate memory bandwidth with nanosecond-scale precision. Overall, MemCoRe presents a promising avenue for efficient memory bandwidth regulation in PS-PL platforms, with strong applicability to real-time systems. ER -
%0 Conference Paper %A Izhbirdeev, Ivan %A Hoornaert, Denis %A Chen, Weifan %A Zuepke, Alexander %A Hammad, Youssef %A Caccamo, Marco %A Mancuso, Renato %T Coherence-Aided Memory Bandwidth Regulation %B 45th IEEE Real-Time Systems Symposium (RTSS 2024) %D 2024 %C York, UK %X With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies. This work explores memory bandwidth regulation in such systems, leveraging the capabilities of tightly coupled FPGAs to offer elegant, low-overhead solutions with highly flexible regulation policies. We introduce MemCoRe, a novel approach that exploits the FPGA’s interaction with cache coherence interfaces and cross-trigger signals to achieve fine-grained spatiotemporal awareness of processor activity and software-free control. By comparing MemCoRe with state-of-the-art software-based approaches, namely MemGuard and MemPol, we demonstrate significant improvements in regulation precision and overhead reduction. Key contributions include nanosecond-scale memory bandwidth regulation, off-core memory bandwidth accounting, address-aware regulation, low-overhead token-bucket regulation, and asymmetric on-off core throttling. Our evaluation on a Xilinx Zynq UltraScale+ ZCU102 CPU+FPGA platform showcases MemCoRe’s capability to regulate memory bandwidth with nanosecond-scale precision. Overall, MemCoRe presents a promising avenue for efficient memory bandwidth regulation in PS-PL platforms, with strong applicability to real-time systems.
[
{
"id": "memcore24",
"type": "paper-conference",
"title": "Coherence-Aided Memory Bandwidth Regulation",
"author": [
{
"family": "Izhbirdeev",
"given": "Ivan"
},
{
"family": "Hoornaert",
"given": "Denis"
},
{
"family": "Chen",
"given": "Weifan"
},
{
"family": "Zuepke",
"given": "Alexander"
},
{
"family": "Hammad",
"given": "Youssef"
},
{
"family": "Caccamo",
"given": "Marco"
},
{
"family": "Mancuso",
"given": "Renato"
}
],
"container-title": "45th IEEE Real-Time Systems Symposium (RTSS 2024)",
"issued": {
"date-parts": [
[
2024,
12
]
]
},
"publisher-place": "York, UK",
"abstract": "With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies. This work explores memory bandwidth regulation in such systems, leveraging the capabilities of tightly coupled FPGAs to offer elegant, low-overhead solutions with highly flexible regulation policies. We introduce MemCoRe, a novel approach that exploits the FPGA’s interaction with cache coherence interfaces and cross-trigger signals to achieve fine-grained spatiotemporal awareness of processor activity and software-free control. By comparing MemCoRe with state-of-the-art software-based approaches, namely MemGuard and MemPol, we demonstrate significant improvements in regulation precision and overhead reduction. Key contributions include nanosecond-scale memory bandwidth regulation, off-core memory bandwidth accounting, address-aware regulation, low-overhead token-bucket regulation, and asymmetric on-off core throttling. Our evaluation on a Xilinx Zynq UltraScale+ ZCU102 CPU+FPGA platform showcases MemCoRe’s capability to regulate memory bandwidth with nanosecond-scale precision. Overall, MemCoRe presents a promising avenue for efficient memory bandwidth regulation in PS-PL platforms, with strong applicability to real-time systems."
}
]
I. Izhbirdeev, D. Hoornaert, W. Chen, A. Zuepke, Y. Hammad, M. Caccamo, and R. Mancuso, “Coherence-Aided Memory Bandwidth Regulation,” in 45th IEEE Real-Time Systems Symposium (RTSS 2024), Dec. 2024.
Izhbirdeev, I., Hoornaert, D., Chen, W., Zuepke, A., Hammad, Y., Caccamo, M., & Mancuso, R. (2024). Coherence-Aided Memory Bandwidth Regulation. In 45th IEEE Real-Time Systems Symposium (RTSS 2024).