Publications Memory & Shared-Resource Management
On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems
16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022), 2022
Abstract
The ever-increasing demand for high-performance in the time-critical embedded domain has pushed the adoption of powerful yet unpredictable heterogeneous Systems-on- a-Chip. The shared memory subsystem, which is known to be a major source of unpredictability, has been extensively studied, and many mitigation techniques have been proposed. Among them, performance-counter-based regulation techniques have seen widespread adoption. However, combining performance-based regulation with time-domain isolation is a relatively unexplored approach that requires the assessment of limitations and benefits. In this article, we outline our current work-in-progress on SHCReg (Software Hardware Co-design Regulator), a full-stack hardware/software co-design architecture that aims to improve the interplay between CPU and memory isolation for mixed-criticality tasks running on the same core.
Code and hardware artifacts
Cite this paper
@inproceedings{SCHREG_OSPERT22,
title = {{On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems}},
author = {Hoornaert, Denis and Ghaemi, Golsana and Bastoni, Andrea and Mancuso, Renato and Caccamo, Marco and Corradi, Giulio},
booktitle = {16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022)},
year = 2022,
url = {https://cs-people.bu.edu/rmancuso/files/papers/SCHREG_OSPERT22.pdf}
}
TY - CONF AU - Hoornaert, Denis AU - Ghaemi, Golsana AU - Bastoni, Andrea AU - Mancuso, Renato AU - Caccamo, Marco AU - Corradi, Giulio TI - On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems T2 - 16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022) PY - 2022 AB - The ever-increasing demand for high-performance in the time-critical embedded domain has pushed the adoption of powerful yet unpredictable heterogeneous Systems-on- a-Chip. The shared memory subsystem, which is known to be a major source of unpredictability, has been extensively studied, and many mitigation techniques have been proposed. Among them, performance-counter-based regulation techniques have seen widespread adoption. However, combining performance-based regulation with time-domain isolation is a relatively unexplored approach that requires the assessment of limitations and benefits. In this article, we outline our current work-in-progress on SHCReg (Software Hardware Co-design Regulator), a full-stack hardware/software co-design architecture that aims to improve the interplay between CPU and memory isolation for mixed-criticality tasks running on the same core. ER -
%0 Conference Paper %A Hoornaert, Denis %A Ghaemi, Golsana %A Bastoni, Andrea %A Mancuso, Renato %A Caccamo, Marco %A Corradi, Giulio %T On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems %B 16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022) %D 2022 %X The ever-increasing demand for high-performance in the time-critical embedded domain has pushed the adoption of powerful yet unpredictable heterogeneous Systems-on- a-Chip. The shared memory subsystem, which is known to be a major source of unpredictability, has been extensively studied, and many mitigation techniques have been proposed. Among them, performance-counter-based regulation techniques have seen widespread adoption. However, combining performance-based regulation with time-domain isolation is a relatively unexplored approach that requires the assessment of limitations and benefits. In this article, we outline our current work-in-progress on SHCReg (Software Hardware Co-design Regulator), a full-stack hardware/software co-design architecture that aims to improve the interplay between CPU and memory isolation for mixed-criticality tasks running on the same core.
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"abstract": "The ever-increasing demand for high-performance in the time-critical embedded domain has pushed the adoption of powerful yet unpredictable heterogeneous Systems-on- a-Chip. The shared memory subsystem, which is known to be a major source of unpredictability, has been extensively studied, and many mitigation techniques have been proposed. Among them, performance-counter-based regulation techniques have seen widespread adoption. However, combining performance-based regulation with time-domain isolation is a relatively unexplored approach that requires the assessment of limitations and benefits. In this article, we outline our current work-in-progress on SHCReg (Software Hardware Co-design Regulator), a full-stack hardware/software co-design architecture that aims to improve the interplay between CPU and memory isolation for mixed-criticality tasks running on the same core."
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D. Hoornaert, G. Ghaemi, A. Bastoni, R. Mancuso, M. Caccamo, and G. Corradi, “On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems,” in 16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022), 2022.
Hoornaert, D., Ghaemi, G., Bastoni, A., Mancuso, R., Caccamo, M., & Corradi, G. (2022). On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems. In 16th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2022).