CPSLab Cyber-Physical Systems Lab, Boston University

Publications Memory & Shared-Resource Management

Identifying Unexpected Inter-core Interference Induced by Shared Cache

Denis Hoornaert, Shahin Roozkhosh, Renato Mancuso, Marco Caccamo

WiP Session @ 27th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2021), May 2021, Online

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Fig. 1: Schematic view of the considered setup with the partitioning of the core cluster (both cores and LLC) on the left, the different path taken by the transactions highlighted in cyan, orange and red, and the AXI-Regulator on the right.

Abstract

In modern real-time multicore systems, understanding and adequately managing shared caches is essential to ensure the temporal isolation of critical tasks. Recent research has identified and extensively studied the sources of unpredictability imputable to shared caches, heavily promoting techniques such as cache partitioning and internal resources management. In this article, we highlight the existence of an enigmatic source of inter-core interference: the CPU-brainfreeze. Experiments realized on a development board show that benchmarks (selected from the San-Diego Vision Benchmark Suite) can exhibit up to a 10-fold increase in their execution time. The same experiment shows that for extreme cases, the core cluster can be stalled indefinitely.

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Cite this paper

@inproceedings{brainfreeze_RTAS_wip_21,
  title     = {{Identifying Unexpected Inter-core Interference Induced by Shared Cache}},
  author    = {Hoornaert, Denis and Roozkhosh, Shahin and Mancuso, Renato and Caccamo, Marco},
  booktitle = {WiP Session @ 27th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2021)},
  year      = 2021,
  month     = may,
  address   = {Online},
  url       = {https://cs-people.bu.edu/rmancuso/files/papers/CPU_Brainfreeze_RTAS21_WiP.pdf}
}

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