Publications Memory & Shared-Resource Management
Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness
36th Euromicro Conference on Real-Time Systems (ECRTS 2024), July 2024, Lille, France
Abstract
Microcontrollers (MCUs) are steadily embracing multi-core technology to meet growing performance demands. This trend marks a shift from their traditionally simple, deterministic designs to more complex and inherently less predictable architectures. While shared resource contention is well-studied in mid to high-end embedded systems, the emergence of multi-core architectures in MCUs introduces unique challenges and characteristics that existing research has not fully explored. In this paper, we conduct an in-depth investigation of both mainstream and next-generation MCU-based platforms, aiming to identify the sources of contention on systems typically lacking these problems. We empirically demonstrate substantial contention effects across different MCU architectures (i.e., from single- to multi-core configurations), highlighting significant application slowdowns. Notably, we observe that slowdowns can reach several orders of magnitude, with the most extreme cases showing up to a 3800x (times, not percent) increase in execution time. To address these issues, we propose and evaluate µTPArtc, a novel mechanism designed for Timely Progress Assessment (TPA) and TPA-based runtime control specifically tailored to MCUs. µTPArtc is an MCU-specialized TPA-based mechanism that leverages hardware facilities widely available in commercial off-the-shelf MCUs (i.e., hardware breakpoints and cycle counters) to successfully monitor applications’ progress, detect, and mitigate timing violations. Our results demonstrate that µTPArtc effectively manages performance degradation due to interference, requiring only minimal modifications to the build pipeline and no changes to the source code of the target application, while incurring minor overheads.
Code and hardware artifacts
Cite this paper
@inproceedings{uTPA_ECRTS24,
title = {{Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness}},
author = {Oliveira, Daniel and Chen, Weifan and Pinto, Sandro and Mancuso, Renato},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
year = 2024,
month = jul,
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Lille, France},
doi = {10.4230/LIPIcs.ECRTS.2024.5},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2024.5}
}
TY - CONF AU - Oliveira, Daniel AU - Chen, Weifan AU - Pinto, Sandro AU - Mancuso, Renato TI - Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness T2 - 36th Euromicro Conference on Real-Time Systems (ECRTS 2024) PY - 2024 DA - 2024/07// PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Lille, France DO - 10.4230/LIPIcs.ECRTS.2024.5 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2024.5 AB - Microcontrollers (MCUs) are steadily embracing multi-core technology to meet growing performance demands. This trend marks a shift from their traditionally simple, deterministic designs to more complex and inherently less predictable architectures. While shared resource contention is well-studied in mid to high-end embedded systems, the emergence of multi-core architectures in MCUs introduces unique challenges and characteristics that existing research has not fully explored. In this paper, we conduct an in-depth investigation of both mainstream and next-generation MCU-based platforms, aiming to identify the sources of contention on systems typically lacking these problems. We empirically demonstrate substantial contention effects across different MCU architectures (i.e., from single- to multi-core configurations), highlighting significant application slowdowns. Notably, we observe that slowdowns can reach several orders of magnitude, with the most extreme cases showing up to a 3800x (times, not percent) increase in execution time. To address these issues, we propose and evaluate µTPArtc, a novel mechanism designed for Timely Progress Assessment (TPA) and TPA-based runtime control specifically tailored to MCUs. µTPArtc is an MCU-specialized TPA-based mechanism that leverages hardware facilities widely available in commercial off-the-shelf MCUs (i.e., hardware breakpoints and cycle counters) to successfully monitor applications’ progress, detect, and mitigate timing violations. Our results demonstrate that µTPArtc effectively manages performance degradation due to interference, requiring only minimal modifications to the build pipeline and no changes to the source code of the target application, while incurring minor overheads. ER -
%0 Conference Paper %A Oliveira, Daniel %A Chen, Weifan %A Pinto, Sandro %A Mancuso, Renato %T Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness %B 36th Euromicro Conference on Real-Time Systems (ECRTS 2024) %D 2024 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Lille, France %R 10.4230/LIPIcs.ECRTS.2024.5 %U https://doi.org/10.4230/LIPIcs.ECRTS.2024.5 %X Microcontrollers (MCUs) are steadily embracing multi-core technology to meet growing performance demands. This trend marks a shift from their traditionally simple, deterministic designs to more complex and inherently less predictable architectures. While shared resource contention is well-studied in mid to high-end embedded systems, the emergence of multi-core architectures in MCUs introduces unique challenges and characteristics that existing research has not fully explored. In this paper, we conduct an in-depth investigation of both mainstream and next-generation MCU-based platforms, aiming to identify the sources of contention on systems typically lacking these problems. We empirically demonstrate substantial contention effects across different MCU architectures (i.e., from single- to multi-core configurations), highlighting significant application slowdowns. Notably, we observe that slowdowns can reach several orders of magnitude, with the most extreme cases showing up to a 3800x (times, not percent) increase in execution time. To address these issues, we propose and evaluate µTPArtc, a novel mechanism designed for Timely Progress Assessment (TPA) and TPA-based runtime control specifically tailored to MCUs. µTPArtc is an MCU-specialized TPA-based mechanism that leverages hardware facilities widely available in commercial off-the-shelf MCUs (i.e., hardware breakpoints and cycle counters) to successfully monitor applications’ progress, detect, and mitigate timing violations. Our results demonstrate that µTPArtc effectively manages performance degradation due to interference, requiring only minimal modifications to the build pipeline and no changes to the source code of the target application, while incurring minor overheads.
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"DOI": "10.4230/LIPIcs.ECRTS.2024.5",
"abstract": "Microcontrollers (MCUs) are steadily embracing multi-core technology to meet growing performance demands. This trend marks a shift from their traditionally simple, deterministic designs to more complex and inherently less predictable architectures. While shared resource contention is well-studied in mid to high-end embedded systems, the emergence of multi-core architectures in MCUs introduces unique challenges and characteristics that existing research has not fully explored. In this paper, we conduct an in-depth investigation of both mainstream and next-generation MCU-based platforms, aiming to identify the sources of contention on systems typically lacking these problems. We empirically demonstrate substantial contention effects across different MCU architectures (i.e., from single- to multi-core configurations), highlighting significant application slowdowns. Notably, we observe that slowdowns can reach several orders of magnitude, with the most extreme cases showing up to a 3800x (times, not percent) increase in execution time. To address these issues, we propose and evaluate µTPArtc, a novel mechanism designed for Timely Progress Assessment (TPA) and TPA-based runtime control specifically tailored to MCUs. µTPArtc is an MCU-specialized TPA-based mechanism that leverages hardware facilities widely available in commercial off-the-shelf MCUs (i.e., hardware breakpoints and cycle counters) to successfully monitor applications’ progress, detect, and mitigate timing violations. Our results demonstrate that µTPArtc effectively manages performance degradation due to interference, requiring only minimal modifications to the build pipeline and no changes to the source code of the target application, while incurring minor overheads."
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D. Oliveira, W. Chen, S. Pinto, and R. Mancuso, “Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness,” in 36th Euromicro Conference on Real-Time Systems (ECRTS 2024), Jul. 2024, doi: 10.4230/LIPIcs.ECRTS.2024.5.
Oliveira, D., Chen, W., Pinto, S., & Mancuso, R. (2024). Shared Resource Contention in Low-end MCUs: A Reality Check and the Quest for Timeliness. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2024.5