Publications Memory & Shared-Resource Management
MemPol: Policing Core Memory Bandwidth from Outside of the Cores
29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023), May 2023, San Antonio, Texas, USA
Abstract
In today’s multiprocessor systems-on-a-chip (MP- SoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102 platform using the SD-VBS.
Cite this paper
@inproceedings{MemPol23,
title = {{MemPol: Policing Core Memory Bandwidth from Outside of the Cores}},
author = {Zuepke, Alexander and Bastoni, Andrea and Chen, Weifan and Caccamo, Marco and Mancuso, Renato},
booktitle = {29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023)},
year = 2023,
month = may,
pages = {235--248},
address = {San Antonio, Texas, USA},
doi = {10.1109/RTAS58335.2023.00026},
url = {https://doi.org/10.1109/RTAS58335.2023.00026}
}
TY - CONF AU - Zuepke, Alexander AU - Bastoni, Andrea AU - Chen, Weifan AU - Caccamo, Marco AU - Mancuso, Renato TI - MemPol: Policing Core Memory Bandwidth from Outside of the Cores T2 - 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023) PY - 2023 DA - 2023/05// CY - San Antonio, Texas, USA SP - 235 EP - 248 DO - 10.1109/RTAS58335.2023.00026 UR - https://doi.org/10.1109/RTAS58335.2023.00026 AB - In today’s multiprocessor systems-on-a-chip (MP- SoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102 platform using the SD-VBS. ER -
%0 Conference Paper %A Zuepke, Alexander %A Bastoni, Andrea %A Chen, Weifan %A Caccamo, Marco %A Mancuso, Renato %T MemPol: Policing Core Memory Bandwidth from Outside of the Cores %B 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023) %D 2023 %P 235-248 %C San Antonio, Texas, USA %R 10.1109/RTAS58335.2023.00026 %U https://doi.org/10.1109/RTAS58335.2023.00026 %X In today’s multiprocessor systems-on-a-chip (MP- SoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102 platform using the SD-VBS.
[
{
"id": "MemPol23",
"type": "paper-conference",
"title": "MemPol: Policing Core Memory Bandwidth from Outside of the Cores",
"author": [
{
"family": "Zuepke",
"given": "Alexander"
},
{
"family": "Bastoni",
"given": "Andrea"
},
{
"family": "Chen",
"given": "Weifan"
},
{
"family": "Caccamo",
"given": "Marco"
},
{
"family": "Mancuso",
"given": "Renato"
}
],
"container-title": "29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023)",
"issued": {
"date-parts": [
[
2023,
5
]
]
},
"page": "235-248",
"publisher-place": "San Antonio, Texas, USA",
"DOI": "10.1109/RTAS58335.2023.00026",
"abstract": "In today’s multiprocessor systems-on-a-chip (MP- SoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102 platform using the SD-VBS."
}
]
A. Zuepke, A. Bastoni, W. Chen, M. Caccamo, and R. Mancuso, “MemPol: Policing Core Memory Bandwidth from Outside of the Cores,” in 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023), pp. 235–248, May. 2023, doi: 10.1109/RTAS58335.2023.00026.
Zuepke, A., Bastoni, A., Chen, W., Caccamo, M., & Mancuso, R. (2023). MemPol: Policing Core Memory Bandwidth from Outside of the Cores. In 29th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2023) (pp. 235–248). https://doi.org/10.1109/RTAS58335.2023.00026