Publications Memory & Shared-Resource Management
MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation
Real-Time Systems, May 2024
Abstract
In today’s multiprocessor systems-on-a-chip (MPSoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.
Code and hardware artifacts
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RT-Bench Software Used or cited in this paper
An extensible framework that turns existing benchmarks into periodic real-time workloads. -
bench (memory bandwidth benchmark) Software Used or cited in this paper
Linux tool that keeps memory traffic running and reports bandwidth with performance-counter data.
Cite this paper
@article{MemPol_RTSJ24,
title = {{MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation}},
author = {Zuepke, Alexander and Bastoni, Andrea and Chen, Weifan and Caccamo, Marco and Mancuso, Renato},
journal = {Real-Time Systems},
year = 2024,
month = may,
publisher = {Springer},
url = {https://cs-people.bu.edu/rmancuso/files/papers/MemPol_RTSJ24.pdf}
}
TY - JOUR AU - Zuepke, Alexander AU - Bastoni, Andrea AU - Chen, Weifan AU - Caccamo, Marco AU - Mancuso, Renato TI - MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation JO - Real-Time Systems PY - 2024 DA - 2024/05// PB - Springer AB - In today’s multiprocessor systems-on-a-chip (MPSoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite. ER -
%0 Journal Article %A Zuepke, Alexander %A Bastoni, Andrea %A Chen, Weifan %A Caccamo, Marco %A Mancuso, Renato %T MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation %J Real-Time Systems %D 2024 %I Springer %X In today’s multiprocessor systems-on-a-chip (MPSoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.
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"abstract": "In today’s multiprocessor systems-on-a-chip (MPSoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time (WCET) analysis. One of the most practical techniques to mitigate interference is memory regulation via throttling. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and carry out an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite."
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A. Zuepke, A. Bastoni, W. Chen, M. Caccamo, and R. Mancuso, “MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation,” Real-Time Systems, May. 2024.
Zuepke, A., Bastoni, A., Chen, W., Caccamo, M., & Mancuso, R. (2024). MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation. Real-Time Systems. Springer.