Publications Memory & Shared-Resource Management
Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs
ACM Trans. Embed. Comput. Syst., March 2023
Abstract
Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard processing cores with programmable logic (PL) for high-performance computing applications. In this paper, we take a deep look into these commercially available heterogeneous platforms and show how to design mixed-criticality applications such that different processing components can be isolated to avoid contention on the shared resources such as last-level cache and main memory. Our approach involves software/hardware co-design to achieve isolation between the different criticality domains. At the hardware level, we use a scratchpad memory (SPM) with dedicated interfaces inside the PL to avoid conflicts in the main memory. Whereas, at the software level, we employ a hypervisor to support cache-coloring such that conflicts at the shared L2 cache can be avoided. In order to move the tasks in/out of the SPM memory, we rely on a DMA engine and propose a new CPU-DMA co-scheduling policy, called Lazy Load, for which we also derive the response time analysis. The results of a case study on image processing demonstrate that the contention on the shared memory subsystem can be avoided when running with our proposed architecture. Moreover, comprehensive schedulability evaluations show that the newly proposed Lazy Load policy outperforms the existing CPU-DMA scheduling approaches and is effective in mitigating the main memory interference in our proposed architecture.
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Cite this paper
@article{LazyLoad_TECS23,
title = {{Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs}},
author = {Kloda, Tomasz and Gracioli, Giovani and Tabish, Rohan and Mirosanlou, Reza and Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco},
journal = {ACM Trans. Embed. Comput. Syst.},
year = 2023,
month = mar,
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
doi = {10.1145/3587694},
url = {https://doi.org/10.1145/3587694}
}
TY - JOUR AU - Kloda, Tomasz AU - Gracioli, Giovani AU - Tabish, Rohan AU - Mirosanlou, Reza AU - Mancuso, Renato AU - Pellizzoni, Rodolfo AU - Caccamo, Marco TI - Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs JO - ACM Trans. Embed. Comput. Syst. PY - 2023 DA - 2023/03// PB - Association for Computing Machinery CY - New York, NY, USA DO - 10.1145/3587694 UR - https://doi.org/10.1145/3587694 AB - Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard processing cores with programmable logic (PL) for high-performance computing applications. In this paper, we take a deep look into these commercially available heterogeneous platforms and show how to design mixed-criticality applications such that different processing components can be isolated to avoid contention on the shared resources such as last-level cache and main memory. Our approach involves software/hardware co-design to achieve isolation between the different criticality domains. At the hardware level, we use a scratchpad memory (SPM) with dedicated interfaces inside the PL to avoid conflicts in the main memory. Whereas, at the software level, we employ a hypervisor to support cache-coloring such that conflicts at the shared L2 cache can be avoided. In order to move the tasks in/out of the SPM memory, we rely on a DMA engine and propose a new CPU-DMA co-scheduling policy, called Lazy Load, for which we also derive the response time analysis. The results of a case study on image processing demonstrate that the contention on the shared memory subsystem can be avoided when running with our proposed architecture. Moreover, comprehensive schedulability evaluations show that the newly proposed Lazy Load policy outperforms the existing CPU-DMA scheduling approaches and is effective in mitigating the main memory interference in our proposed architecture. ER -
%0 Journal Article %A Kloda, Tomasz %A Gracioli, Giovani %A Tabish, Rohan %A Mirosanlou, Reza %A Mancuso, Renato %A Pellizzoni, Rodolfo %A Caccamo, Marco %T Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs %J ACM Trans. Embed. Comput. Syst. %D 2023 %I Association for Computing Machinery %C New York, NY, USA %R 10.1145/3587694 %U https://doi.org/10.1145/3587694 %X Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard processing cores with programmable logic (PL) for high-performance computing applications. In this paper, we take a deep look into these commercially available heterogeneous platforms and show how to design mixed-criticality applications such that different processing components can be isolated to avoid contention on the shared resources such as last-level cache and main memory. Our approach involves software/hardware co-design to achieve isolation between the different criticality domains. At the hardware level, we use a scratchpad memory (SPM) with dedicated interfaces inside the PL to avoid conflicts in the main memory. Whereas, at the software level, we employ a hypervisor to support cache-coloring such that conflicts at the shared L2 cache can be avoided. In order to move the tasks in/out of the SPM memory, we rely on a DMA engine and propose a new CPU-DMA co-scheduling policy, called Lazy Load, for which we also derive the response time analysis. The results of a case study on image processing demonstrate that the contention on the shared memory subsystem can be avoided when running with our proposed architecture. Moreover, comprehensive schedulability evaluations show that the newly proposed Lazy Load policy outperforms the existing CPU-DMA scheduling approaches and is effective in mitigating the main memory interference in our proposed architecture.
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"abstract": "Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard processing cores with programmable logic (PL) for high-performance computing applications. In this paper, we take a deep look into these commercially available heterogeneous platforms and show how to design mixed-criticality applications such that different processing components can be isolated to avoid contention on the shared resources such as last-level cache and main memory. Our approach involves software/hardware co-design to achieve isolation between the different criticality domains. At the hardware level, we use a scratchpad memory (SPM) with dedicated interfaces inside the PL to avoid conflicts in the main memory. Whereas, at the software level, we employ a hypervisor to support cache-coloring such that conflicts at the shared L2 cache can be avoided. In order to move the tasks in/out of the SPM memory, we rely on a DMA engine and propose a new CPU-DMA co-scheduling policy, called Lazy Load, for which we also derive the response time analysis. The results of a case study on image processing demonstrate that the contention on the shared memory subsystem can be avoided when running with our proposed architecture. Moreover, comprehensive schedulability evaluations show that the newly proposed Lazy Load policy outperforms the existing CPU-DMA scheduling approaches and is effective in mitigating the main memory interference in our proposed architecture."
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T. Kloda, G. Gracioli, R. Tabish, R. Mirosanlou, R. Mancuso, R. Pellizzoni, and M. Caccamo, “Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs,” ACM Trans. Embed. Comput. Syst., Mar. 2023, doi: 10.1145/3587694.
Kloda, T., Gracioli, G., Tabish, R., Mirosanlou, R., Mancuso, R., Pellizzoni, R., & Caccamo, M. (2023). Lazy Load Scheduling for Mixed-Criticality Applications in Heterogeneous MPSoCs. ACM Trans. Embed. Comput. Syst.. Association for Computing Machinery. https://doi.org/10.1145/3587694