Publications Memory & Shared-Resource Management
Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms
31th Euromicro Conference on Real-Time Systems (ECRTS 2019), July 2019, Stuttgart, Germany
Outstanding Paper Award
Abstract
Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application.
Cite this paper
@inproceedings{mixcrit_mpsoc_ECRTS19,
title = {{Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms}},
author = {Gracioli, Giovani and Tabish, Rohan and Mancuso, Renato and Mirosanlou, Reza and Pellizzoni, Rodolfo and Caccamo, Marco},
booktitle = {31th Euromicro Conference on Real-Time Systems (ECRTS 2019)},
year = 2019,
month = jul,
volume = {107},
pages = {27:1--27:25},
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Stuttgart, Germany},
doi = {10.4230/LIPIcs.ECRTS.2019.27},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2019.27},
note = {Outstanding Paper Award}
}
TY - CONF AU - Gracioli, Giovani AU - Tabish, Rohan AU - Mancuso, Renato AU - Mirosanlou, Reza AU - Pellizzoni, Rodolfo AU - Caccamo, Marco TI - Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms T2 - 31th Euromicro Conference on Real-Time Systems (ECRTS 2019) PY - 2019 DA - 2019/07// VL - 107 PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Stuttgart, Germany SP - 27:1 EP - 27:25 DO - 10.4230/LIPIcs.ECRTS.2019.27 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2019.27 AB - Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application. ER -
%0 Conference Paper %A Gracioli, Giovani %A Tabish, Rohan %A Mancuso, Renato %A Mirosanlou, Reza %A Pellizzoni, Rodolfo %A Caccamo, Marco %T Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms %B 31th Euromicro Conference on Real-Time Systems (ECRTS 2019) %D 2019 %V 107 %P 27:1-27:25 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Stuttgart, Germany %R 10.4230/LIPIcs.ECRTS.2019.27 %U https://doi.org/10.4230/LIPIcs.ECRTS.2019.27 %X Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application.
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"abstract": "Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application."
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G. Gracioli, R. Tabish, R. Mancuso, R. Mirosanlou, R. Pellizzoni, and M. Caccamo, “Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms,” in 31th Euromicro Conference on Real-Time Systems (ECRTS 2019), vol. 107, pp. 27:1–27:25, Jul. 2019, doi: 10.4230/LIPIcs.ECRTS.2019.27.
Gracioli, G., Tabish, R., Mancuso, R., Mirosanlou, R., Pellizzoni, R., & Caccamo, M. (2019). Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms. In 31th Euromicro Conference on Real-Time Systems (ECRTS 2019) (pp. 27:1–27:25). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2019.27