Publications Memory & Shared-Resource Management
Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications
, 2019, Munich, Germany
Abstract
Systems-on-a-Chip (SoC) devices integrating hard processing cores with programmable logic (PL) are becoming increasingly available. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at COTS-based heterogeneous SoCs that incorporates PL and a multicore processor. We show how one can tailor these processors to support a mixed/full criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in LLC, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation SoC platform, and show results based on both a set of data intensive tasks, as well as a complete case study based on an anomaly detection application for an autonomous vehicle. recently the co-location of traditional CPUs and programmable logic (PL) implemented using Field Programmable Gate Array (FPGA) technology. The presence of on-chip “soft” PL, tightly coupled with a group of “hard” embedded CPUs, represents a game-changer for systems that need to be tailored to a well-known application scenario. This is indeed often the case for real-time systems. In fact, this new class of platforms offer the unprecedented ability to define new hardware components to complement the high-performance profile of the embedded cores. If it is possible to devise PL-defined components that mitigate the non-determinism in high-performance CPUs, the result can be an ideal trade-off between processing power and real-time guarantees. In this paper, we study how it is possible to leverage latest-generation partially reconfigurable embedded platforms for a system design that combines high-performance and strict real-time requirements. In our approach, we define multiple criticality domains to be intended as sub-shells of the
Cite this paper
@inproceedings{SPM_Stream_Techrep,
title = {{Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications}},
author = {Gracioli, Giovani and Tabish, Rohan and Mirosanlou, Reza and Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco},
year = 2019,
publisher = {Technical University of Munich (TUM)},
address = {Munich, Germany},
url = {https://mediatum.ub.tum.de/doc/1475015/1475015.pdf}
}
TY - CONF AU - Gracioli, Giovani AU - Tabish, Rohan AU - Mirosanlou, Reza AU - Mancuso, Renato AU - Pellizzoni, Rodolfo AU - Caccamo, Marco TI - Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications T2 - PY - 2019 PB - Technical University of Munich (TUM) CY - Munich, Germany AB - Systems-on-a-Chip (SoC) devices integrating hard processing cores with programmable logic (PL) are becoming increasingly available. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at COTS-based heterogeneous SoCs that incorporates PL and a multicore processor. We show how one can tailor these processors to support a mixed/full criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in LLC, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation SoC platform, and show results based on both a set of data intensive tasks, as well as a complete case study based on an anomaly detection application for an autonomous vehicle. recently the co-location of traditional CPUs and programmable logic (PL) implemented using Field Programmable Gate Array (FPGA) technology. The presence of on-chip “soft” PL, tightly coupled with a group of “hard” embedded CPUs, represents a game-changer for systems that need to be tailored to a well-known application scenario. This is indeed often the case for real-time systems. In fact, this new class of platforms offer the unprecedented ability to define new hardware components to complement the high-performance profile of the embedded cores. If it is possible to devise PL-defined components that mitigate the non-determinism in high-performance CPUs, the result can be an ideal trade-off between processing power and real-time guarantees. In this paper, we study how it is possible to leverage latest-generation partially reconfigurable embedded platforms for a system design that combines high-performance and strict real-time requirements. In our approach, we define multiple criticality domains to be intended as sub-shells of the ER -
%0 Conference Paper %A Gracioli, Giovani %A Tabish, Rohan %A Mirosanlou, Reza %A Mancuso, Renato %A Pellizzoni, Rodolfo %A Caccamo, Marco %T Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications %B %D 2019 %I Technical University of Munich (TUM) %C Munich, Germany %X Systems-on-a-Chip (SoC) devices integrating hard processing cores with programmable logic (PL) are becoming increasingly available. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at COTS-based heterogeneous SoCs that incorporates PL and a multicore processor. We show how one can tailor these processors to support a mixed/full criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in LLC, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation SoC platform, and show results based on both a set of data intensive tasks, as well as a complete case study based on an anomaly detection application for an autonomous vehicle. recently the co-location of traditional CPUs and programmable logic (PL) implemented using Field Programmable Gate Array (FPGA) technology. The presence of on-chip “soft” PL, tightly coupled with a group of “hard” embedded CPUs, represents a game-changer for systems that need to be tailored to a well-known application scenario. This is indeed often the case for real-time systems. In fact, this new class of platforms offer the unprecedented ability to define new hardware components to complement the high-performance profile of the embedded cores. If it is possible to devise PL-defined components that mitigate the non-determinism in high-performance CPUs, the result can be an ideal trade-off between processing power and real-time guarantees. In this paper, we study how it is possible to leverage latest-generation partially reconfigurable embedded platforms for a system design that combines high-performance and strict real-time requirements. In our approach, we define multiple criticality domains to be intended as sub-shells of the
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"abstract": "Systems-on-a-Chip (SoC) devices integrating hard processing cores with programmable logic (PL) are becoming increasingly available. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at COTS-based heterogeneous SoCs that incorporates PL and a multicore processor. We show how one can tailor these processors to support a mixed/full criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in LLC, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation SoC platform, and show results based on both a set of data intensive tasks, as well as a complete case study based on an anomaly detection application for an autonomous vehicle. recently the co-location of traditional CPUs and programmable logic (PL) implemented using Field Programmable Gate Array (FPGA) technology. The presence of on-chip “soft” PL, tightly coupled with a group of “hard” embedded CPUs, represents a game-changer for systems that need to be tailored to a well-known application scenario. This is indeed often the case for real-time systems. In fact, this new class of platforms offer the unprecedented ability to define new hardware components to complement the high-performance profile of the embedded cores. If it is possible to devise PL-defined components that mitigate the non-determinism in high-performance CPUs, the result can be an ideal trade-off between processing power and real-time guarantees. In this paper, we study how it is possible to leverage latest-generation partially reconfigurable embedded platforms for a system design that combines high-performance and strict real-time requirements. In our approach, we define multiple criticality domains to be intended as sub-shells of the"
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G. Gracioli, R. Tabish, R. Mirosanlou, R. Mancuso, R. Pellizzoni, and M. Caccamo, “Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications,” in , 2019.
Gracioli, G., Tabish, R., Mirosanlou, R., Mancuso, R., Pellizzoni, R., & Caccamo, M. (2019). Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time Event-Triggered Applications. In . Technical University of Munich (TUM).