Publications Memory & Shared-Resource Management
An analyzable inter-core communication framework for high-performance multicore embedded systems
Journal of Systems Architecture, 2021
Abstract
Multicore processors provide great average-case performance. However, the use of multicore processors for safety-critical applications can lead to catastrophic consequences because of contention on shared resources. The problem has been well-studied in literature, and solutions such as partitioning of shared resources have been proposed. Strict partitioning of memory resources among cores, however, does not allow intercore communication. This paper proposes a Communication Core Model (CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multicore system. A system-level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive the WCET of the tasks using CCM is provided. We compare our proposed CCM with Contention-based Communication (CBC), where no private banking is enforced for any core. The analytical approach results using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent compared to the CBC. Moreover, our experimental results indicate that the measured WCET using SD-VBS is within the bounds calculated using the proposed analysis.
Cite this paper
@article{TABISH2021102178,
title = {{An analyzable inter-core communication framework for high-performance multicore embedded systems}},
author = {Tabish, Rohan and Wen, Jen-Yang and Pellizzoni, Rodolfo and Mancuso, Renato and Yun, Heechul and Caccamo, Marco and Sha, Lui},
journal = {Journal of Systems Architecture},
year = 2021,
pages = {102178},
doi = {10.1016/j.sysarc.2021.102178},
url = {https://doi.org/10.1016/j.sysarc.2021.102178}
}
TY - JOUR AU - Tabish, Rohan AU - Wen, Jen-Yang AU - Pellizzoni, Rodolfo AU - Mancuso, Renato AU - Yun, Heechul AU - Caccamo, Marco AU - Sha, Lui TI - An analyzable inter-core communication framework for high-performance multicore embedded systems JO - Journal of Systems Architecture PY - 2021 SP - 102178 DO - 10.1016/j.sysarc.2021.102178 UR - https://doi.org/10.1016/j.sysarc.2021.102178 AB - Multicore processors provide great average-case performance. However, the use of multicore processors for safety-critical applications can lead to catastrophic consequences because of contention on shared resources. The problem has been well-studied in literature, and solutions such as partitioning of shared resources have been proposed. Strict partitioning of memory resources among cores, however, does not allow intercore communication. This paper proposes a Communication Core Model (CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multicore system. A system-level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive the WCET of the tasks using CCM is provided. We compare our proposed CCM with Contention-based Communication (CBC), where no private banking is enforced for any core. The analytical approach results using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent compared to the CBC. Moreover, our experimental results indicate that the measured WCET using SD-VBS is within the bounds calculated using the proposed analysis. ER -
%0 Journal Article %A Tabish, Rohan %A Wen, Jen-Yang %A Pellizzoni, Rodolfo %A Mancuso, Renato %A Yun, Heechul %A Caccamo, Marco %A Sha, Lui %T An analyzable inter-core communication framework for high-performance multicore embedded systems %J Journal of Systems Architecture %D 2021 %P 102178 %R 10.1016/j.sysarc.2021.102178 %U https://doi.org/10.1016/j.sysarc.2021.102178 %X Multicore processors provide great average-case performance. However, the use of multicore processors for safety-critical applications can lead to catastrophic consequences because of contention on shared resources. The problem has been well-studied in literature, and solutions such as partitioning of shared resources have been proposed. Strict partitioning of memory resources among cores, however, does not allow intercore communication. This paper proposes a Communication Core Model (CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multicore system. A system-level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive the WCET of the tasks using CCM is provided. We compare our proposed CCM with Contention-based Communication (CBC), where no private banking is enforced for any core. The analytical approach results using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent compared to the CBC. Moreover, our experimental results indicate that the measured WCET using SD-VBS is within the bounds calculated using the proposed analysis.
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"abstract": "Multicore processors provide great average-case performance. However, the use of multicore processors for safety-critical applications can lead to catastrophic consequences because of contention on shared resources. The problem has been well-studied in literature, and solutions such as partitioning of shared resources have been proposed. Strict partitioning of memory resources among cores, however, does not allow intercore communication. This paper proposes a Communication Core Model (CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multicore system. A system-level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive the WCET of the tasks using CCM is provided. We compare our proposed CCM with Contention-based Communication (CBC), where no private banking is enforced for any core. The analytical approach results using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent compared to the CBC. Moreover, our experimental results indicate that the measured WCET using SD-VBS is within the bounds calculated using the proposed analysis."
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R. Tabish, J. Y. Wen, R. Pellizzoni, R. Mancuso, H. Yun, M. Caccamo, and L. Sha, “An analyzable inter-core communication framework for high-performance multicore embedded systems,” Journal of Systems Architecture, pp. 102178, 2021, doi: 10.1016/j.sysarc.2021.102178.
Tabish, R., Wen, J. Y., Pellizzoni, R., Mancuso, R., Yun, H., Caccamo, M., & Sha, L. (2021). An analyzable inter-core communication framework for high-performance multicore embedded systems. Journal of Systems Architecture, 102178. https://doi.org/10.1016/j.sysarc.2021.102178