Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC

@inproceedings{mpsoc_mem_ospert18,
  title     = {{Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC}},
  author    = {Bansal, Ayoosh and Tabish, Rohan and Gracioli, Giovani and Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco},
  booktitle = {14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018)},
  year      = 2018,
  month     = jul,
  pages     = {55--60},
  address   = {Barcelona, Spain},
  url       = {https://cs-people.bu.edu/rmancuso/files/papers/mpsoc_mem_OSPERT18.pdf}
}

CopyDownload .bib

TY  - CONF
AU  - Bansal, Ayoosh
AU  - Tabish, Rohan
AU  - Gracioli, Giovani
AU  - Mancuso, Renato
AU  - Pellizzoni, Rodolfo
AU  - Caccamo, Marco
TI  - Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC
T2  - 14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018)
PY  - 2018
DA  - 2018/07//
CY  - Barcelona, Spain
SP  - 55
EP  - 60
AB  - This paper presents the evaluation of the memory subsystem of the Xilinx Ultrascale+ MPSoC. The characteristics of various memories in the system are evaluated using carefully instrumented micro-benchmarks. The impact of micro-architectural features like caches, prefetchers and cache-coherency are measured and discussed. The impact of multi-core contention on shared memory resources is evaluated. Finally, proposals are made for the design of mixed-criticality real-time applications on this platform.
ER  - 

CopyDownload .ris

%0 Conference Paper
%A Bansal, Ayoosh
%A Tabish, Rohan
%A Gracioli, Giovani
%A Mancuso, Renato
%A Pellizzoni, Rodolfo
%A Caccamo, Marco
%T Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC
%B 14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018)
%D 2018
%P 55-60
%C Barcelona, Spain
%X This paper presents the evaluation of the memory subsystem of the Xilinx Ultrascale+ MPSoC. The characteristics of various memories in the system are evaluated using carefully instrumented micro-benchmarks. The impact of micro-architectural features like caches, prefetchers and cache-coherency are measured and discussed. The impact of multi-core contention on shared memory resources is evaluated. Finally, proposals are made for the design of mixed-criticality real-time applications on this platform.

CopyDownload .enw

[
    {
        "id": "mpsoc_mem_ospert18",
        "type": "paper-conference",
        "title": "Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC",
        "author": [
            {
                "family": "Bansal",
                "given": "Ayoosh"
            },
            {
                "family": "Tabish",
                "given": "Rohan"
            },
            {
                "family": "Gracioli",
                "given": "Giovani"
            },
            {
                "family": "Mancuso",
                "given": "Renato"
            },
            {
                "family": "Pellizzoni",
                "given": "Rodolfo"
            },
            {
                "family": "Caccamo",
                "given": "Marco"
            }
        ],
        "container-title": "14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018)",
        "issued": {
            "date-parts": [
                [
                    2018,
                    7
                ]
            ]
        },
        "page": "55-60",
        "publisher-place": "Barcelona, Spain",
        "abstract": "This paper presents the evaluation of the memory subsystem of the Xilinx Ultrascale+ MPSoC. The characteristics of various memories in the system are evaluated using carefully instrumented micro-benchmarks. The impact of micro-architectural features like caches, prefetchers and cache-coherency are measured and discussed. The impact of multi-core contention on shared memory resources is evaluated. Finally, proposals are made for the design of mixed-criticality real-time applications on this platform."
    }
]

CopyDownload .json

A. Bansal, R. Tabish, G. Gracioli, R. Mancuso, R. Pellizzoni, and M. Caccamo, “Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC,” in 14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018), pp. 55–60, Jul. 2018.

CopyDownload .txt

Bansal, A., Tabish, R., Gracioli, G., Mancuso, R., Pellizzoni, R., & Caccamo, M. (2018). Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC. In 14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 2018) (pp. 55–60).

CopyDownload .txt