Publications Memory & Shared-Resource Management
WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment
29th Euromicro Conference on Real-Time Systems (ECRTS 2017), June 2017, Dubrovnik, Croatia
Abstract
In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores’ budgets. In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art.
Cite this paper
@inproceedings{mg_explicit_ECRTS17,
title = {{WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment}},
author = {Mancuso, Renato and Pellizzoni, Rodolfo and Tokcan, Neriman and Caccamo, Marco},
booktitle = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
year = 2017,
month = jun,
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Dubrovnik, Croatia},
doi = {10.4230/LIPIcs.ECRTS.2017.3},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2017.3}
}
TY - CONF AU - Mancuso, Renato AU - Pellizzoni, Rodolfo AU - Tokcan, Neriman AU - Caccamo, Marco TI - WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment T2 - 29th Euromicro Conference on Real-Time Systems (ECRTS 2017) PY - 2017 DA - 2017/06// PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Dubrovnik, Croatia DO - 10.4230/LIPIcs.ECRTS.2017.3 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2017.3 AB - In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores’ budgets. In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art. ER -
%0 Conference Paper %A Mancuso, Renato %A Pellizzoni, Rodolfo %A Tokcan, Neriman %A Caccamo, Marco %T WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment %B 29th Euromicro Conference on Real-Time Systems (ECRTS 2017) %D 2017 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Dubrovnik, Croatia %R 10.4230/LIPIcs.ECRTS.2017.3 %U https://doi.org/10.4230/LIPIcs.ECRTS.2017.3 %X In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores’ budgets. In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art.
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"DOI": "10.4230/LIPIcs.ECRTS.2017.3",
"abstract": "In the last decade there has been a steady uptrend in the popularity of embedded multi-core platforms. This represents a turning point in the theory and implementation of real-time systems. From a real-time standpoint, however, the extensive sharing of hardware resources (e.g. caches, DRAM subsystem, I/O channels) represents a major source of unpredictability. Budget-based memory regulation (throttling) has been extensively studied to enforce a strict partitioning of the DRAM subsystem’s bandwidth. The common approach to analyze a task under memory bandwidth regulation is to consider the budget of the core where the task is executing, and assume the worst-case about the remaining cores’ budgets. In this work, we propose a novel analysis strategy to derive the WCET of a task under memory bandwidth regulation that takes into account the exact distribution of memory budgets to cores. In this sense, the proposed analysis represents a generalization of approaches that consider (i) even budget distribution across cores; and (ii) uneven but unknown (except for the core under analysis) budget assignment. By exploiting the additional piece of information, we show that it is possible to derive a more accurate WCET estimation. Our evaluations highlight that the proposed technique can reduce overestimation by 30% in average, and up to 60%, compared to the state of the art."
}
]
R. Mancuso, R. Pellizzoni, N. Tokcan, and M. Caccamo, “WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment,” in 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), Jun. 2017, doi: 10.4230/LIPIcs.ECRTS.2017.3.
Mancuso, R., Pellizzoni, R., Tokcan, N., & Caccamo, M. (2017). WCET Derivation Under Single Core Equivalence With Explicit Memory Budget Assignment. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2017.3