Publications Memory & Shared-Resource Management
A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems
Real-Time Systems, October 2019
Abstract
Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O operations in time domain can be enforced, and (iii) how predictable asynchronous inter/intra-core communication between tasks can be performed. To validate the proposed design, we implemented the proposed OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results show that novel design delivers predictable temporal behavior to hard real-time tasks, and it provides performance gain of upto 2.1 × compared to traditional approaches.
Cite this paper
@article{spm_os_journal,
title = {{A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems}},
author = {Tabish, Rohan and Mancuso, Renato and Wasly, Saud and Pellizzoni, Rodolfo and Caccamo, Marco},
journal = {Real-Time Systems},
year = 2019,
month = oct,
volume = {55},
number = {4},
pages = {850--888},
publisher = {Springer Netherlands},
doi = {10.1007/s11241-019-09340-0},
url = {https://doi.org/10.1007/s11241-019-09340-0}
}
TY - JOUR AU - Tabish, Rohan AU - Mancuso, Renato AU - Wasly, Saud AU - Pellizzoni, Rodolfo AU - Caccamo, Marco TI - A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems JO - Real-Time Systems PY - 2019 DA - 2019/10// VL - 55 IS - 4 PB - Springer Netherlands SP - 850 EP - 888 DO - 10.1007/s11241-019-09340-0 UR - https://doi.org/10.1007/s11241-019-09340-0 AB - Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O operations in time domain can be enforced, and (iii) how predictable asynchronous inter/intra-core communication between tasks can be performed. To validate the proposed design, we implemented the proposed OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results show that novel design delivers predictable temporal behavior to hard real-time tasks, and it provides performance gain of upto 2.1 × compared to traditional approaches. ER -
%0 Journal Article %A Tabish, Rohan %A Mancuso, Renato %A Wasly, Saud %A Pellizzoni, Rodolfo %A Caccamo, Marco %T A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems %J Real-Time Systems %D 2019 %V 55 %N 4 %P 850-888 %I Springer Netherlands %R 10.1007/s11241-019-09340-0 %U https://doi.org/10.1007/s11241-019-09340-0 %X Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O operations in time domain can be enforced, and (iii) how predictable asynchronous inter/intra-core communication between tasks can be performed. To validate the proposed design, we implemented the proposed OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results show that novel design delivers predictable temporal behavior to hard real-time tasks, and it provides performance gain of upto 2.1 × compared to traditional approaches.
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"abstract": "Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O operations in time domain can be enforced, and (iii) how predictable asynchronous inter/intra-core communication between tasks can be performed. To validate the proposed design, we implemented the proposed OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results show that novel design delivers predictable temporal behavior to hard real-time tasks, and it provides performance gain of upto 2.1 × compared to traditional approaches."
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R. Tabish, R. Mancuso, S. Wasly, R. Pellizzoni, and M. Caccamo, “A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems,” Real-Time Systems, vol. 55, no. 4, pp. 850–888, Oct. 2019, doi: 10.1007/s11241-019-09340-0.
Tabish, R., Mancuso, R., Wasly, S., Pellizzoni, R., & Caccamo, M. (2019). A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems. Real-Time Systems, 55(4), 850–888. Springer Netherlands. https://doi.org/10.1007/s11241-019-09340-0