CPSLab Cyber-Physical Systems Lab, Boston University

Publications Memory & Shared-Resource Management

A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems

Rohan Tabish, Renato Mancuso, Saud Wasly, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo

23rd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017), April 2017, Pittsburgh, PA, USA

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Fig. 1.

Abstract

The reliable use of multi-core platforms for designing safety-critical systems still represents an open challenge. Recently, the FAA [1] has formally expressed its concern towards the use of multi-core systems in avionics. The sharing of hardware resources introduces non-trivial timing dependencies between logically independent components (e.g. cores); additionally, the increase in size of circuitry, memory resources, and transistor density makes these platforms more susceptible to transient memory (soft) errors. This work addresses the problem of memory soft errors and their recovery at an OS/platform level on commercial multi-core systems. Proposed strategy considers the schedulability impact of recovery procedures on hard real-time workloads. Finally, the implementation of a SPM-centric OS with the proposed OS-level strategies was performed by using a commercially available multi-core platform. The design has been validated and evaluated using a combination of synthetic and realistic (EEMBC) benchmarks.

Cite this paper

@inproceedings{spm_os_rec_RTAS17,
  title     = {{A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems}},
  author    = {Tabish, Rohan and Mancuso, Renato and Wasly, Saud and Phatak, Sujit S. and Pellizzoni, Rodolfo and Caccamo, Marco},
  booktitle = {23rd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017)},
  year      = 2017,
  month     = apr,
  address   = {Pittsburgh, PA, USA},
  url       = {https://cs-people.bu.edu/rmancuso/files/papers/spm_os_rec_RTAS17.pdf}
}

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