Publications Real-Time Virtualization
Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems
25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019), April 2019, Montreal, Canada
Abstract
One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.
Cite this paper
@inproceedings{virtIDArtas19,
title = {{Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems}},
author = {Kloda, Tomasz and Solieri, Marco and Mancuso, Renato and Capodieci, Nicola and Valente, Paolo and Bertogna, Marko},
booktitle = {25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019)},
year = 2019,
month = apr,
pages = {1--14},
address = {Montreal, Canada},
doi = {10.1109/RTAS.2019.00009},
url = {https://doi.org/10.1109/RTAS.2019.00009}
}
TY - CONF AU - Kloda, Tomasz AU - Solieri, Marco AU - Mancuso, Renato AU - Capodieci, Nicola AU - Valente, Paolo AU - Bertogna, Marko TI - Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems T2 - 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019) PY - 2019 DA - 2019/04// CY - Montreal, Canada SP - 1 EP - 14 DO - 10.1109/RTAS.2019.00009 UR - https://doi.org/10.1109/RTAS.2019.00009 AB - One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks. ER -
%0 Conference Paper %A Kloda, Tomasz %A Solieri, Marco %A Mancuso, Renato %A Capodieci, Nicola %A Valente, Paolo %A Bertogna, Marko %T Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems %B 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019) %D 2019 %P 1-14 %C Montreal, Canada %R 10.1109/RTAS.2019.00009 %U https://doi.org/10.1109/RTAS.2019.00009 %X One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.
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"abstract": "One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks."
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T. Kloda, M. Solieri, R. Mancuso, N. Capodieci, P. Valente, and M. Bertogna, “Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems,” in 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019), pp. 1–14, Apr. 2019, doi: 10.1109/RTAS.2019.00009.
Kloda, T., Solieri, M., Mancuso, R., Capodieci, N., Valente, P., & Bertogna, M. (2019). Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems. In 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2019) (pp. 1–14). https://doi.org/10.1109/RTAS.2019.00009