Publications Real-Time Virtualization
The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs
36th Euromicro Conference on Real-Time Systems (ECRTS 2024), July 2024, Lille, France
Abstract
Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, including enabling the seamless launch of virtual machines on different ISAs and extending spatial/temporal isolation to heterogenous cores with enhanced regulation policies.
Code and hardware artifacts
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RT-Bench Software Used or cited in this paper
An extensible framework that turns existing benchmarks into periodic real-time workloads. -
Jailhouse-RT Software Used or cited in this paper
A fork of the Jailhouse partitioning hypervisor with experimental real-time features. -
Omnivisor Software Introduced in this paper
Static partitioning hypervisor extension that manages asymmetric cores on MPSoCs.
Cite this paper
@inproceedings{Omnivisor_ECRTS24,
title = {{The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs}},
author = {Ottaviano, Daniele and Ciraolo, Francesco and Mancuso, Renato and Cinque, Marcello},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
year = 2024,
month = jul,
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Lille, France},
doi = {10.4230/LIPIcs.ECRTS.2024.6},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2024.6}
}
TY - CONF AU - Ottaviano, Daniele AU - Ciraolo, Francesco AU - Mancuso, Renato AU - Cinque, Marcello TI - The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs T2 - 36th Euromicro Conference on Real-Time Systems (ECRTS 2024) PY - 2024 DA - 2024/07// PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Lille, France DO - 10.4230/LIPIcs.ECRTS.2024.6 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2024.6 AB - Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, including enabling the seamless launch of virtual machines on different ISAs and extending spatial/temporal isolation to heterogenous cores with enhanced regulation policies. ER -
%0 Conference Paper %A Ottaviano, Daniele %A Ciraolo, Francesco %A Mancuso, Renato %A Cinque, Marcello %T The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs %B 36th Euromicro Conference on Real-Time Systems (ECRTS 2024) %D 2024 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Lille, France %R 10.4230/LIPIcs.ECRTS.2024.6 %U https://doi.org/10.4230/LIPIcs.ECRTS.2024.6 %X Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, including enabling the seamless launch of virtual machines on different ISAs and extending spatial/temporal isolation to heterogenous cores with enhanced regulation policies.
[
{
"id": "Omnivisor_ECRTS24",
"type": "paper-conference",
"title": "The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs",
"author": [
{
"family": "Ottaviano",
"given": "Daniele"
},
{
"family": "Ciraolo",
"given": "Francesco"
},
{
"family": "Mancuso",
"given": "Renato"
},
{
"family": "Cinque",
"given": "Marcello"
}
],
"container-title": "36th Euromicro Conference on Real-Time Systems (ECRTS 2024)",
"issued": {
"date-parts": [
[
2024,
7
]
]
},
"publisher": "Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik",
"publisher-place": "Lille, France",
"DOI": "10.4230/LIPIcs.ECRTS.2024.6",
"abstract": "Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, including enabling the seamless launch of virtual machines on different ISAs and extending spatial/temporal isolation to heterogenous cores with enhanced regulation policies."
}
]
D. Ottaviano, F. Ciraolo, R. Mancuso, and M. Cinque, “The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs,” in 36th Euromicro Conference on Real-Time Systems (ECRTS 2024), Jul. 2024, doi: 10.4230/LIPIcs.ECRTS.2024.6.
Ottaviano, D., Ciraolo, F., Mancuso, R., & Cinque, M. (2024). The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2024.6