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Deterministic Memory Abstraction and Supporting Multicore System Architecture
30th Euromicro Conference on Real-Time Systems (ECRTS 2018), July 2018, Barcelona, Spain
Abstract
Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform–the OS and hardware–guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.
Code and hardware artifacts
Cite this paper
@inproceedings{detmem_ECRTS18,
title = {{Deterministic Memory Abstraction and Supporting Multicore System Architecture}},
author = {Farshchi, Farzad and Valsan, Prathap Kumar and Mancuso, Renato and Yun, Heechul},
booktitle = {30th Euromicro Conference on Real-Time Systems (ECRTS 2018)},
year = 2018,
month = jul,
publisher = {Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik},
address = {Barcelona, Spain},
doi = {10.4230/LIPIcs.ECRTS.2018.1},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2018.1}
}
TY - CONF AU - Farshchi, Farzad AU - Valsan, Prathap Kumar AU - Mancuso, Renato AU - Yun, Heechul TI - Deterministic Memory Abstraction and Supporting Multicore System Architecture T2 - 30th Euromicro Conference on Real-Time Systems (ECRTS 2018) PY - 2018 DA - 2018/07// PB - Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik CY - Barcelona, Spain DO - 10.4230/LIPIcs.ECRTS.2018.1 UR - https://doi.org/10.4230/LIPIcs.ECRTS.2018.1 AB - Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform–the OS and hardware–guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach. ER -
%0 Conference Paper %A Farshchi, Farzad %A Valsan, Prathap Kumar %A Mancuso, Renato %A Yun, Heechul %T Deterministic Memory Abstraction and Supporting Multicore System Architecture %B 30th Euromicro Conference on Real-Time Systems (ECRTS 2018) %D 2018 %I Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik %C Barcelona, Spain %R 10.4230/LIPIcs.ECRTS.2018.1 %U https://doi.org/10.4230/LIPIcs.ECRTS.2018.1 %X Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform–the OS and hardware–guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.
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"abstract": "Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform–the OS and hardware–guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach."
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F. Farshchi, P. K. Valsan, R. Mancuso, and H. Yun, “Deterministic Memory Abstraction and Supporting Multicore System Architecture,” in 30th Euromicro Conference on Real-Time Systems (ECRTS 2018), Jul. 2018, doi: 10.4230/LIPIcs.ECRTS.2018.1.
Farshchi, F., Valsan, P. K., Mancuso, R., & Yun, H. (2018). Deterministic Memory Abstraction and Supporting Multicore System Architecture. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.ECRTS.2018.1