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Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems
arXiv preprint arXiv:1707.05260, October 2017
Abstract
Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform—the OS and hardware—guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.
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Cite this paper
@article{farshchi2017deterministic,
title = {{Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems}},
author = {Farshchi, Farzad and Valsan, Prathap Kumar and Mancuso, Renato and Yun, Heechul},
journal = {arXiv preprint arXiv:1707.05260},
year = 2017,
month = oct,
publisher = {University of Kansas (KU)},
address = {Lawrence, KS, USA},
url = {https://arxiv.org/pdf/1707.05260}
}
TY - JOUR AU - Farshchi, Farzad AU - Valsan, Prathap Kumar AU - Mancuso, Renato AU - Yun, Heechul TI - Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems JO - arXiv preprint arXiv:1707.05260 PY - 2017 DA - 2017/10// PB - University of Kansas (KU) CY - Lawrence, KS, USA AB - Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform—the OS and hardware—guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach. ER -
%0 Journal Article %A Farshchi, Farzad %A Valsan, Prathap Kumar %A Mancuso, Renato %A Yun, Heechul %T Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems %J arXiv preprint arXiv:1707.05260 %D 2017 %I University of Kansas (KU) %C Lawrence, KS, USA %X Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform—the OS and hardware—guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.
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"abstract": "Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform—the OS and hardware—guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach."
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F. Farshchi, P. K. Valsan, R. Mancuso, and H. Yun, “Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems,” arXiv preprint arXiv:1707.05260, Oct. 2017.
Farshchi, F., Valsan, P. K., Mancuso, R., & Yun, H. (2017). Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems. arXiv preprint arXiv:1707.05260. University of Kansas (KU).