Memory Wedding Problem

Finding Best Memory Match!



The escalating demand for high-performance real-time systems has pushed embedded hardware vendors to integrate heterogeneous computing resources onto the same chip. In lockstep with computing resources, memory resources have also increased in heterogeneity, with modern SoCs featuring multiple memory technologies including DRAM, SRAM, multi-level caches, BRAM, and NVM memories, to name a few. Different memory technologies have distinct temporal characteristics and are the concretization of a different equilibrium point in the cost vs. performance trade-off.

We propose to (1) profile page importance in time-sensitive applications, (2) assess the performance characteristics of each memory technology, and (3) provide both profiling information to the OS to make informed decisions on the allocation of each application page.



Miscellaneous Resources

Matchmaking Real-Time Applications


June, 2021

Governing with Insights: Towards Profile-Driven Cache Management of Black-Box Applications

Sep, 2022
Code Milestone

Add kernel level tools to manage memory placement.

Sep, 2022
Code Milestone

Heuristic to decide the suitable memory partner.