PLIM: Programmable Logic In the Middle

Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions.

Perfect Translator
Loop-back through PL. Green line with the Translator in the middle is a valid memory loop-back. Dashed red line results in an endless loop. Two logic analyzer probes (ILA) are attached to monitor the bus segments.

We proposed, implemented, and evaluated a first technique, Cache Bleaching, that leverages PLIM to solve long-standing shortcomings of page-coloring-based cache partitioning.

with PLIM

(1) What is the overhead for transactions that are routed through the Memory Loop-Back as opposed to reaching main memory directly?

(2) What type of management can be enacted with PLIM?

(3) How can memory traffic be dynamically routed via/away from a PLIM module?

We demonstrate that under PLIM it is possible to obtain an unprecedented level of inspection on the behavior of last-level caches (LLC) and main memory

Fragmented DRAM

With the Bleacher (right), colored addresses are de-colored hence, previously scattered pages (left) become contiguous in DRAM

Contiguous DRAM with PLIM

We implement and evaluate a full-stack design that includes hardware modules and hypervisor-level adaptations to take advantage of the newly available control over LLC partitioning at runtime

Zynq UltraScale+ MPSoC ZCU102 Platrofm